3D Chip Pad Structure for Probe Mark Removal and Stacking

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Solution Overview

Problem

Existing chip probing methods cause irreversible damage to metal connection pads, leading to probe marks that affect electrical performance and heat dissipation, and limit the number of stackable layers in multi-chip packages.

Innovation Solution

A chip design with a separate metal probing pad and connection vias allows for independent chip probing and 3D interconnection, where the probe mark is removed and filled with a dielectric material, maintaining electrical connectivity and reducing the thickness of the stacking interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the same metal connection pad is used for both probing and 3D interconnection, then device complexity is reduced, but the metal connection pad suffers irreversible damage causing probe marks that degrade electrical performance and heat dissipation

Engineering Contradiction:

Improvestructure complexityVSAvoidelectrical performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent divides the originally unified metal connection pad into two separate components: a metal connection pad for 3D interconnection and a metal probing pad for probing operations. This segmentation allows each component to perform its specific function without interfering with the other, preventing probe marks from damaging the interconnection structure while maintaining electrical performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The probing function is extracted from the metal connection pad by introducing a separate metal probing pad. This extraction removes the harmful probing action from the interconnection path, allowing the metal connection pad to remain intact for reliable 3D interconnection while the metal probing pad absorbs the probing damage.

Inventive Principle:

Principle #2Taking out (Extraction)

2Ease of manufacture

If probe marks are buried using a medium layer, then the raised probe mark is covered, but the medium layer thickness must be excessively large which is inconducive to stacking of multiple chip layers and causes heat dissipation problems

Engineering Contradiction:

Improveprobe mark processingVSAvoidheat dissipation

Core Design Contradiction:

Ease of manufactureVSTemperature

Solution Approach 1:

Instead of burying the probe mark with a thick medium layer, the patent extracts the probing function to a separate metal probing pad. The probe mark is then removed through etching and the area is filled with a medium filling structure, eliminating the need for an excessively thick medium layer and preserving heat dissipation pathways for multi-chip stacking.

Inventive Principle:

Principle #2Taking out (Extraction)

3Manufacturing precision

If the raised probe mark is removed through etching, then the probe mark is eliminated, but over-etching occurs causing removal of the metal connection pad and loss of electrical connection

Engineering Contradiction:

Improveprobe mark removal precisionVSAvoidelectrical connection

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the pad structure into a metal connection pad and a metal probing pad. The etching process is then applied only to the metal probing pad area, which is spatially separated from the metal connection pad. This segmentation allows precise removal of probe marks from the probing pad without risking over-etching damage to the interconnection structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a medium filling structure as an intermediary element that fills the area where the metal probing pad was removed. This mediator protects the underlying metal connection pad from over-etching damage while allowing complete removal of the probe mark from the probing pad area.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Ease of manufacture

If a thick medium layer is used to bury the probe mark, then the probe mark is covered, but the stacking interface thickness increases limiting the number of stackable chip layers

Engineering Contradiction:

Improveprobe mark processingVSAvoidstacking interface thickness

Core Design Contradiction:

Ease of manufactureVSLength of stationary object

Solution Approach 1:

The patent extracts the probing function to a separate metal probing pad and removes the probe mark through etching followed by filling with a medium filling structure. This approach eliminates the need for a thick medium layer, reducing the stacking interface thickness and enabling greater numbers of chip layers to be stacked.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250336731A1Chip, Chip Fabricating Method, Multi-Chip Stacking Package, and Electronic Device

Publication Date: 2025.10.30 HUAWEI TECH CO LTD

AI summary

A chip includes a metal connection pad, a plurality of first connection vias, a plurality of second connection vias, a first metal wire, a medium filling structure, and a first medium layer. The metal connection pad is electrically coupled to the first metal wire through the first connection vias. The medium filling structure and the metal connection pad are disposed at a same layer. The second connection vias are located between the medium filling structure and the first metal wire and are electrically coupled to the first metal wire. The first medium layer covers the metal connection pad, the first medium layer has a window area at a position corresponding to the medium filling structure, and the window area is filled with a dielectric material.