Semiconductor Chip Pad Relocation for Wiring Design Freedom
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Solution Overview
Problem
The arrangement of chip pads in semiconductor devices limits design freedom and increases the total size of the chip, as they are typically placed in the middle region, restricting the wiring design for electrical connections in the peripheral region.
Innovation Solution
The semiconductor device incorporates a substrate with a cell region and a circuit region, featuring a secondary uppermost wiring layer with an uppermost chip pad in the cell region and a redistribution wiring layer connected to an external connector, allowing for a more efficient layout that reduces the chip size and enhances design freedom by shifting the uppermost chip pad from the circuit region to the cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If chip pads are arranged in the middle region of the semiconductor device, then electrical connection is established, but the total size of the chip increases and design freedom of wirings is limited
Solution Approach 1:
The patent moves the uppermost chip pad from the circuit region to the cell region, utilizing the spatial dimension of the cell region for pad placement. This dimensional relocation allows wiring designs to extend into the cell region, increasing design freedom while potentially reducing the overall chip size by more efficiently utilizing available space.
Solution Approach 2:
The patent divides the semiconductor device into distinct regions (circuit region and cell region) with specific functional assignments. By segmenting the device structure and assigning the uppermost chip pad to the cell region while keeping other wirings in the circuit region, the design enables independent optimization of each region's function and space utilization.
2Adaptability or versatility
If chip pads are arranged in the middle region, then electrical connection is established, but wiring design flexibility in the peripheral region is restricted
Solution Approach 1:
The invention utilizes the cell region as an additional spatial dimension for placing the uppermost chip pad, which enables wirings to be designed more flexibly by extending into this region. This dimensional approach provides greater adaptability for wiring configurations without proportionally increasing the overall chip area.
Solution Approach 2:
The patent applies different functional qualities to different regions: the circuit region contains the secondary uppermost wiring and circuit patterns, while the cell region contains the uppermost chip pad. This local differentiation allows each region to be optimized for its specific function, enhancing overall wiring design flexibility.
3Productivity
If uppermost chip pad is placed in the circuit region, then electrical connection is established, but the layout efficiency is reduced
Solution Approach 1:
The patent segments the device into circuit region and cell region with distinct functional assignments. By placing the uppermost chip pad in the cell region rather than the circuit region, the layout achieves better efficiency by preventing pad-wiring overlap and enabling more compact arrangement of circuit elements.
Solution Approach 2:
The invention relocates the uppermost chip pad to the cell region, utilizing this spatial dimension for optimized layout. This dimensional reassignment improves layout efficiency by separating pad placement from circuit wiring, allowing independent optimization of both elements within their respective regions.
Data Source
AI summary
A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.