Chip Interconnect Pad Layout for Self-Aligned Multi-Chip Bonding
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Solution Overview
Problem
Existing multi-chip interconnection technologies face challenges in achieving precise alignment bonding due to installation errors during the packaging process of semiconductor chips.
Innovation Solution
A method for forming chip packages involves arranging a chipset with first and second chips on a carrier, forming bumps on the chips, and using an interconnect device with first and second pads to align and bond with the bumps, allowing for self-alignment of the second pads with larger accommodating error spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional alignment bonding methods are used for multi-chip interconnection, then bonding precision is required to be very high, but installation errors during packaging process make alignment bonding difficult to realize
Solution Approach 1:
The patent introduces an interconnect device as an intermediary component between chips. This device includes a first substrate bonded to a first chip, and a second substrate bonded to a second chip. The interconnect device mediates the connection between chips, allowing independent bonding processes for each chip-substrate pair, thereby eliminating the need for simultaneous multi-chip alignment and reducing the impact of installation errors on bonding precision.
Solution Approach 2:
The patent segments the multi-chip interconnection process into independent chip-substrate bonding operations. Instead of bonding multiple chips to a single substrate simultaneously (which requires high precision alignment), each chip is bonded to its own substrate in separate operations. This segmentation allows each bonding process to tolerate installation errors independently, significantly improving bonding reliability.
2Quantity of substance
If high-density bump arrays are used to increase interconnection density, then manufacturing complexity increases, but installation errors become more difficult to accommodate
Solution Approach 1:
The patent divides the high-density bump array into separate groups on different substrates. Each substrate carries a portion of the bumps, and bonding operations are performed independently for each substrate-chip pair. This segmentation allows the system to achieve high overall interconnection density while each individual bonding operation maintains relaxed alignment tolerances, accommodating installation errors effectively.
Data Source
AI summary
The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.