Chip Package Pad Layout for Bonding Stress Transfer

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Solution Overview

Problem

The bonding process between semiconductor packages and substrates often experiences reduced yield due to bonding stress, which can damage insulating layers and affect the integrity of the chip package structure.

Innovation Solution

A chip package structure is formed with a conductive pad having a first portion passing through a barrier layer and a second portion passing through an insulating layer, with a conductive bump formed over the second portion, allowing bonding stress to be directly conducted to the barrier layer and substrate, thereby protecting the insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bonding process is performed between package and substrate, then the chip package structure is formed, but the bonding stress damages the insulating layer and reduces yield

Engineering Contradiction:
Improvebonding yieldVSAvoidbonding stress damage to insulating layer
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The conductive pad is divided into two distinct portions: a first portion that contacts the insulating layer and a second portion that contacts the barrier layer. This segmentation allows the bonding stress to be directed to the barrier layer through the second portion, while the first portion remains protected from direct stress exposure, preventing insulating layer damage and improving bonding yield

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second portion of the conductive pad acts as an intermediary element between the conductive bump and the barrier layer. It provides a dedicated stress transmission path that mediates the bonding stress, directing it to the more resilient barrier layer rather than allowing it to directly impact the insulating layer, thus protecting the insulating layer while maintaining bonding integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the conductive pad structure is modified to protect insulating layer, then bonding yield improves, but the structural complexity increases

Engineering Contradiction:
Improvebonding yieldVSAvoidconductive pad structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive pad is segmented into two portions with distinct functions, but this segmentation is achieved within a single continuous conductive structure rather than adding separate components. The first portion protects the insulating layer while the second portion transmits stress to the barrier layer, providing protection without significantly increasing overall structural complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conductive pad serves multiple functions: it provides electrical connection, mechanical support, and stress management. By making the conductive pad multi-functional with its two portions, the design achieves insulating layer protection without requiring additional dedicated protective structures, thereby avoiding excessive complexity increase

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the yield of the bonding process by ensuring the insulating layer is not damaged by bonding stress, while maintaining coplanarity of the conductive bumps, resulting in enhanced bonding efficiency.

Implementation Method 1

allowing bonding stress to be directly conducted to the barrier layer and substrate, thereby protecting the insulating layer

Methodology Applied
Scientific EffectStress conduction: Conduction (thermal)

Data Source

PatentUS11855039B2Chip package structure
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11855039B2 patent drawing
  • US11855039B2 patent drawing
  • US11855039B2 patent drawing

AI summary

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.