Semiconductor Chip Pad Layout for Warpage and Crack Relief

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Solution Overview

Problem

Semiconductor devices face challenges in maintaining reliability due to warpage and cracking of semiconductor chips caused by internal stress and thermal expansion, particularly in vertical MOSFETs, which affect the transport and performance of the devices.

Innovation Solution

The semiconductor device incorporates a first connector connected to at least one electrode pad, with additional electrode pads not connected to the first connector, and a sealing resin covering these unconnected pads, along with strategic electrode pad orientations to mitigate internal stress and thermal expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all electrode pads are connected to connectors and wires, then electrical connectivity is ensured, but internal stress and warpage increase due to rigid constraints

Engineering Contradiction:
Improvechip stabilityVSAvoidchip flatness
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by differentiating the treatment of electrode pads: some pads (first electrode pads) are connected to connectors via bonding materials for electrical connectivity, while other pads (second electrode pads) are intentionally left unconnected to serve as stress relief zones. This local differentiation allows the chip to maintain both electrical functionality and mechanical stability by releasing internal stress at specific locations without compromising overall connectivity.

Inventive Principle:
Principle #3Local quality

2Reliability

If rigid connectors and wires are used for all electrode pads, then electrical connection is secure, but thermal expansion causes cracking and reduces reliability

Engineering Contradiction:
Improvedevice durabilityVSAvoidthermal stress damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of thermal expansion into a beneficial stress relief mechanism. By leaving certain electrode pads unconnected, the design allows thermal expansion forces to be absorbed and released through these unconnected regions rather than transmitting cracking stresses through the entire chip structure. The unconnected pads act as sacrificial elements that protect the critical connected pads from thermal damage.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If multiple bonding materials are used for electrical connection, then connectivity is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidbonding structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the electrode pad population into two distinct groups: connected pads for electrical functionality and unconnected pads for stress management. This segmentation simplifies the overall bonding structure by reducing the number of required bonding materials and connectors, while still achieving both electrical connectivity and mechanical stability. The segmented approach avoids the complexity of designing universal bonding solutions for all pads.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability of the semiconductor device by reducing warpage and cracking, ensuring stable transport and improved performance.

Implementation Method 1

warpage and cracking of semiconductor chips caused by internal stress and thermal expansion

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12482728B2Semiconductor device
Publication Date: 2025.11.25 KK TOSHIBA
  • US12482728B2 patent drawing
  • US12482728B2 patent drawing
  • US12482728B2 patent drawing

AI summary

A semiconductor device of an embodiment includes a lead frame; a first bonding material; a semiconductor chip including a lower surface, an upper surface, a first electrode connected to the first bonding material, a second electrode provided on the upper surface, and electrode pads connected to the second electrode; second bonding materials provided on each of the electrode pads; and a first connector connected to at least one of the second bonding materials, wherein the second bonding material which is not connected to the first connector is not connected to a connector or a wire.