Semiconductor Chip Pad Layout to Prevent Test-Induced Wire Cracks
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Solution Overview
Problem
The challenge in semiconductor chip design is to reduce thickness while maintaining reliability, particularly in stacked semiconductor packages with through silicon vias (TSVs), where test pads and bump pads are integrated, and to minimize cracks in wiring during testing.
Innovation Solution
The semiconductor chip design includes a pad metal layer with test pads exposed from a protective layer, and the wiring layers are arranged to avoid overlapping the test pads, reducing the thickness of the pad metal layer and minimizing wire cracks by eliminating wire overlap under the test pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pad metal layer is made thick to ensure structural integrity and reliable electrical connection, then the reliability is improved, but the chip thickness increases
Solution Approach 1:
The pad metal layer is extended in the lateral direction (first or second direction) rather than increasing its thickness in the vertical direction. This dimensional shift allows the pad to maintain sufficient electrical connection area and structural integrity while keeping the chip thickness reduced, directly resolving the contradiction between reliability and thickness.
2Area of stationary object
If test pads are positioned to overlap with wiring layers for compact layout, then the area is reduced, but cracks may occur in the wiring layers during testing
Solution Approach 1:
The test pad structure is extracted from the overlapping region with the wiring layer. By positioning the test pad such that it does not overlap the wiring layer in the vertical direction, the harmful stress concentration that could cause cracks is eliminated, while the pad still performs its testing function effectively.
Solution Approach 2:
The outer portion of the pad metal layer acts as an intermediary element that provides electrical connection without directly overlapping the wiring layer. This intermediary positioning allows the test signal to be transmitted while preventing mechanical stress from being applied to the fragile wiring layer during testing operations.
3Adaptability or versatility
If multiple layers of wiring are integrated to increase functionality, then the device complexity is improved, but parasitic capacitance and RC delay increase
Solution Approach 1:
The pad metal layer is designed with non-uniform extension in different directions, creating different local properties. The extension in the first direction versus the second direction allows optimization of electrical connection in different regions, managing parasitic capacitance locally rather than uniformly across the entire structure.
Data Source
AI summary
Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.