Semiconductor Chip Passivation Layout for Stronger Molding Adhesion
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and reliable connection of semiconductor chips due to inadequate adhesive force between the molding layer and the semiconductor chip, which affects the stability and performance of the package.
Innovation Solution
The semiconductor chip design includes a passivation layer with an insulating layer and an oxide layer, where the oxide layer has a narrower width than the insulating layer, providing enhanced adhesive force with the molding layer, and the chip pads are surrounded by the passivation layer to improve connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional passivation layer structure is used, then the manufacturing process is simple, but the adhesive force with the molding layer is insufficient
Solution Approach 1:
The passivation layer is constructed as a composite structure comprising an insulating layer and an oxide layer. The insulating layer provides electrical insulation properties, while the oxide layer provides enhanced adhesive force with the molding layer. This composite material approach resolves the contradiction by combining materials with different functional properties to simultaneously achieve both simplicity and high adhesive force.
Solution Approach 2:
The oxide layer is positioned specifically at the interface between the passivation layer and the molding layer, where adhesive force is needed. The insulating layer is positioned where electrical insulation is required. This local quality assignment allows each layer to perform its specific function optimally, resolving the contradiction between adhesive force and structural complexity.
2Strength
If the oxide layer has the same width as the insulating layer, then the structure is symmetric and simple, but the adhesive force with the molding layer is insufficient
Solution Approach 1:
The oxide layer is designed with a different width than the insulating layer, creating an asymmetric structure. Specifically, the oxide layer has a narrower width than the insulating layer, which allows the molding layer to contact both the oxide layer and the insulating layer, thereby enhancing the overall adhesive force. This asymmetric configuration resolves the contradiction between adhesive force and structural simplicity.
3Strength
If the passivation layer covers the entire chip surface, then protection is comprehensive, but the molding layer cannot adequately contact the chip for bonding
Solution Approach 1:
The passivation layer is segmented into two distinct layers with different widths and functions. The narrower oxide layer is positioned to allow molding layer contact, while the wider insulating layer provides comprehensive protection. This segmentation resolves the contradiction by dividing the passivation function into protective and bonding functions performed by different layers.
Solution Approach 2:
The oxide layer acts as an intermediary between the insulating layer and the molding layer. It provides a bonding interface that allows the molding layer to adhere to the passivation structure while the insulating layer maintains comprehensive protection. This intermediary role resolves the contradiction between protection and bonding contact.
Data Source
AI summary
Provided is a semiconductor chip including a semiconductor chip including a semiconductor substrate including a first surface and a second surface opposite to the first surface, a wiring layer arranged on the first surface of the semiconductor substrate, a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, a plurality of chip pads arranged on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes, and a passivation layer arranged on the second surface of the semiconductor substrate and in contact with side surfaces of the plurality of chip pads. The passivation layer includes an insulating layer and an oxide layer arranged on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along the horizontal direction. The first width is greater than the second width.