Chip Performance Estimation Using Neural Network Weight Vectors
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Solution Overview
Problem
Existing methods for estimating chip performance values struggle to accurately account for different process-voltage-temperature (PVT) sensitivities across various chips, leading to inconsistent performance value estimation.
Innovation Solution
A method utilizing neural network models to train on oscillation period vectors, dividing chip sets based on training error, and outputting weight vectors to optimize performance value estimation, ensuring that the product of oscillation period vectors and weight vectors for each divided chip set is maximized compared to others.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single formula is used to estimate chip performance values for all chips, then the estimation process is simple, but the estimation accuracy deteriorates due to different PVT-to-delay sensitivities across chips
Solution Approach 1:
The patent segments the chip set into multiple divided chip sets based on training errors from neural network models. Each divided chip set is assigned a specific weight vector that reflects its unique PVT-to-delay sensitivity characteristics. This segmentation allows the system to move from a single uniform estimation formula to multiple specialized formulas, thereby improving estimation accuracy for each chip group while maintaining systematic simplicity through automated classification.
Solution Approach 2:
The patent applies local quality by assigning different weight vectors to different divided chip sets based on their specific PVT-to-delay sensitivities. Instead of using a universal weight vector for all chips, each chip set receives customized weights that locally optimize the estimation formula for its specific characteristics. This enables high estimation accuracy for each local group while the overall system remains manageable through the neural network-based classification framework.
2Measurement precision
If multiple divided chip sets with different weight vectors are used to account for PVT sensitivities, then estimation accuracy improves, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by using neural network models to pre-train and classify chips into divided chip sets before actual performance estimation. The weight vectors for each divided chip set are predetermined through training on oscillation period vectors and critical path delay data. This preliminary classification and weight assignment simplifies the subsequent estimation process, as the system only needs to identify which divided chip set a chip belongs to and apply the corresponding pre-determined weight vector, rather than performing complex real-time analysis.
Solution Approach 2:
The patent introduces neural network models as intermediaries between the raw chip characteristics (oscillation period vectors) and the final performance estimation. These neural networks automatically learn the complex mappings and classifications, handling the complexity of dividing chips into appropriate sets and determining optimal weight vectors. This intermediary layer absorbs the computational complexity, allowing the actual estimation process to remain relatively simple while achieving high accuracy through the intelligent classification framework.
Data Source
AI summary
A method for estimating performance values of chips includes: (A) using oscillation period vectors of a to-be-divide chip set to train a first neural network model to obtain a training error of the to-be-divided chip set, where in the first-time conducted step (A), the to-be-divided chip set includes the chips; (B) dividing the to-be-divided chip set into divided chip sets according to the training error; and (C) using oscillation period vectors of the divided chip sets as training data of a second neural network model, so that the second neural network model outputs weight vectors respectively corresponding to the divided chip sets. A product of oscillation period vector(s) of each divided chip set and a weight vector of the divided chip set is larger than a product of the oscillation period vector(s) of the divided chip set and a weight vector of each of rest of divided chip sets.