Semiconductor Chip Peripheral Roughening for Delamination Prevention

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Large semiconductor chips experience delamination and structural weakness due to thermal stress and mismatched thermal expansion coefficients between the chip and encapsulant, exacerbated by surface roughening which reduces structural strength and increases the risk of cracks.

Innovation Solution

A semiconductor package design featuring a roughened peripheral portion on the non-active surface of the chip, extending at least one third from the corner to the center, combined with a non-roughened central portion to enhance bonding with the encapsulant while maintaining structural strength, using methods like laser or chemical etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the non-active surface of the semiconductor chip is roughened to enhance bonding with the encapsulant, then delamination is prevented, but the structural strength of the chip is reduced and cracks may occur

Engineering Contradiction:

Improvebonding strength between chip and encapsulantVSAvoidstructural strength of semiconductor chip

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent applies local quality by roughening only the peripheral portion of the non-active surface of the semiconductor chip, while keeping the central portion smooth. This selective roughening enhances bonding at the periphery where delamination is most likely to occur, while preserving the structural strength of the central region that would be weakened by complete surface roughening.

Inventive Principle:

Principle #3Local quality

2Volume of moving object

If the semiconductor chip is thinned for compact packaging, then package size is reduced, but the chip becomes more susceptible to cracks when the surface is roughened

Engineering Contradiction:

Improvepackage sizeVSAvoidstructural strength of thinned chip

Core Design Contradiction:

Volume of moving objectVSStrength

Solution Approach 1:

The patent resolves this contradiction by applying roughening treatment only to the peripheral portion of the thinned chip's non-active surface, preserving the central region's structural integrity. This allows compact packaging with thinned chips while preventing cracks that would result from roughening the entire surface.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the non-active surface into two distinct zones: a peripheral portion subjected to roughening for enhanced bonding, and a central portion maintained smooth for structural strength. This segmentation allows the thinned chip to achieve both compact packaging and resistance to cracking.

Inventive Principle:

Principle #1Segmentation

3Reliability

If the chip size is increased for higher performance, then electrical performance is enhanced, but thermal stress and delamination increase due to greater distance from center to corner

Engineering Contradiction:

Improveelectrical performance of packageVSAvoidthermal stress and delamination at corners

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent addresses thermal stress and delamination in large chips by applying roughening treatment specifically to the peripheral portion where corners are located. This enhances bonding at the most vulnerable regions subjected to greatest thermal stress, while maintaining the chip's overall large size for high electrical performance.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents delamination and structural weakness in large semiconductor chips by reinforcing bonding at the corners while preserving the chip's structural integrity, suitable for compact electronic products.

Implementation Method 1

a roughened structure is formed on a peripheral portion of the non-active surface of the semiconductor chip... the bonding between the semiconductor chip and an encapsulant that encapsulates the semiconductor chip can be enhanced by the roughened structure

Methodology Applied

Scientific EffectMechanical interlocking:

Implementation Method 2

using methods like laser or chemical etching

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Implementation Method 3

using methods like laser or chemical etching

Methodology Applied

Scientific EffectChemical etching:

Data Source

PatentUS8895366B2Fabrication method of semiconductor package

Publication Date: 2014.11.25 SILICONWARE PRECISION IND CO LTD

AI summary

A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.