Chip Placement Using CNN Feature Extraction and Mask Generation
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Solution Overview
Problem
Current chip placement methods are time-consuming and expensive, requiring hardware expertise, and struggle to efficiently place millions of circuit modules while adhering to design constraints such as no overlapping and minimizing wirelength, with existing deep learning techniques not effectively generating position masks and wire masks.
Innovation Solution
A chip placement method using convolutional neural networks to extract local and global features, generate various masks, and determine optimal placement positions, incorporating a reward design scheme to avoid sparse rewards and ensure compliance with design constraints, thereby improving placement efficiency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If deep learning technology is applied to chip placement, then placement efficiency is improved, but the complexity of feature preprocessing and mask generation increases
Solution Approach 1:
The feature extraction process is segmented into distinct components: position mask generation, wire mask generation, and feature map construction. Each component handles a specific aspect of the placement problem, making the overall complex system manageable and efficient
Solution Approach 2:
Position masks and wire masks are generated in advance before the actual placement decision is made. These masks pre-process the geometric and connectivity information, so that when the neural network performs placement, the complex preprocessing work has already been completed
2Measurement precision
If convolutional neural networks with multiple kernel sizes are used, then feature extraction capability is improved, but computational time increases
Solution Approach 1:
The computational process is segmented into parallel operations: position mask generation, wire mask generation, and feature map extraction all occur simultaneously rather than sequentially, reducing total computational time while maintaining multi-scale feature extraction capability
Solution Approach 2:
Instead of using all possible kernel sizes for every placement decision, the system uses a selective approach where different kernel sizes are applied only when relevant to the current placement context, reducing unnecessary computational overhead
3Productivity
If reinforcement learning with dense rewards is implemented, then training convergence is improved, but constraint satisfaction becomes more difficult
Solution Approach 1:
The reward system is segmented into two independent components: a dense reward for placement progress (speeding up convergence) and a separate constraint penalty for violations (ensuring reliability). This segmentation allows both objectives to be optimized simultaneously without conflict
Solution Approach 2:
A constraint penalty mechanism acts as an intermediary between the dense reward signal and the final placement decision. This intermediary ensures that constraint violations are penalized appropriately while allowing the dense reward to drive rapid convergence
Data Source
AI summary
A chip placement method includes the steps of: (a) determining the order of placement of integrated circuit chips by the features of the chip modules, (b) generating pix-level masks from the status of the placed chips and the next two chips to be placed, (c) extracting local and global features from the masks by convolutional neural networks, and (d) selecting the placement position by merged features and a congestion threshold. The method is carried out by computer apparatus with a storage medium.