Chip Placement Image Alignment Using Marking Member Calibration
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Solution Overview
Problem
Conventional chip-placing methods require repeated processes to establish error averages for precise placement, are inefficient in correcting thermal deformation errors, and often necessitate additional alignment patterns, limiting accuracy and precision.
Innovation Solution
A chip-placing method and apparatus that utilize a chip-placing member, a reference-image capturing device, and an alignment-image capture device to obtain relative position information, allowing for real-time calibration and alignment of chip placement on a substrate using a marking member, enabling precise positioning and angle adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional chip-placing method uses repeated processes to establish error averages, then placement accuracy is improved, but production efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-establishing the position calibration relationship between the chip-placing member and substrate before actual chip placement. The error characteristics are measured and compensated in advance, allowing subsequent placements to proceed without repeated measurement cycles, thus improving both accuracy and efficiency
Solution Approach 2:
The patent uses image capturing devices to create optical copies of the marking member and substrate positions. These image data are processed to establish position calibration relationships, replacing physical repeated measurements with computational analysis of captured images, thereby maintaining accuracy while reducing production time
2Manufacturing precision
If conventional method uses average error compensation, then placement precision is improved, but adaptability to new error factors deteriorates
Solution Approach 1:
The patent implements feedback by continuously monitoring the actual positions of marking members and substrates using image capturing devices during the placement process. The system dynamically adjusts the position calibration relationship based on real-time detected deviations, enabling adaptation to new error factors such as thermal deformation while maintaining placement precision
Solution Approach 2:
The patent transforms the static average error compensation into a dynamic position calibration system. The calibration relationship is not fixed but is continuously updated based on real-time image data and detected position deviations, allowing the system to adapt to changing conditions while maintaining precision
3Device complexity
If chip gripper and reference mark are not separately disposed, then device complexity is reduced, but alignment capability deteriorates
Solution Approach 1:
The patent applies segmentation by separating the chip gripper and reference mark into distinct, independently disposed components. This spatial separation allows the image capturing device to clearly distinguish and separately image both the marking member on the substrate and the chip being placed, thereby achieving high alignment capability without requiring complex integrated structures
Data Source
AI summary
A chip-placing method for performing an image alignment of chip placement comprises a chip pick-up step, a reference-image capturing step, an alignment-image capturing step, a calculating and processing step, a calibration adjusting step and a placing step. An image(s) of a marking member and a chip sucked by a chip-placing member is/are captured from an opposite direction so as to obtain a relative position information of the chip in relation to the marking member. An image showing the marking member and the substrate is captured from a backside so as to obtain a relative position information of the marking member in relation to the substrate. A position calibration relationship information of the position of the chip in relation to a to-be-placed location of the substrate is obtained according to those relative position information. Therefore, a relative position of the chip-placing member in relation to the to-be-placed location is calibrated.