Chip Power Domain Timing Dependency Analysis
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Solution Overview
Problem
Current low-power chip design methods may cause instability in chip circuits when switching off power domains without considering timing dependency between power domains, leading to potential circuit instability.
Innovation Solution
A chip design method and device that determine timing dependency between power domains during the RTL verification stage, using a power management unit to isolate affected power domains before switching off, ensuring stability by analyzing control signals and power supply relationships to identify and manage timing dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power domains are switched off without considering timing dependency, then power consumption is reduced, but circuit stability deteriorates
Solution Approach 1:
The patent applies preliminary action by performing timing dependency analysis during the RTL verification stage before actual chip fabrication and operation. This early analysis identifies which power domains have timing dependencies on others, allowing the design to pre-establish isolation mechanisms and control signal coordination strategies. When power domains are subsequently switched off, the system can follow pre-determined safe switching sequences that maintain circuit stability while achieving power savings.
2Reliability
If timing dependency analysis is performed during RTL verification stage, then circuit stability is improved, but design complexity increases
Solution Approach 1:
The patent applies self-service by leveraging the existing RTL verification infrastructure and tools already present in the chip design flow. The timing dependency analysis is integrated into the conventional RTL verification stage, reusing existing simulation environments, testbenches, and verification methodologies. This approach allows the design to perform comprehensive timing analysis without requiring separate complex analysis tools or processes, thereby reducing the increase in design complexity while still achieving improved circuit stability.
Data Source
AI summary
A chip design method, a chip design device, a chip, and an electronic device are provided. The chip design method includes: determining at least one power state of the chip, one power state of the at least one power state including switch states of respective power domains on the chip in a chip operation mode, and the at least one power state including a first power state; determining control signals sent by changed power domains in the respective power domains in a case where a power state of the chip is switched to the first power state, in a case where the power state of the chip is switched to the first power state, switch states of the changed power domains changing; and analyzing timing dependency between the control signals to determine timing dependency between power domains to which the control signals act in the first power state.