Mainboard Chip Power Layout for Low-Impedance Dynamic Response
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Solution Overview
Problem
The existing power supply structures on mainboards face challenges in meeting the dynamic response requirements of future processor chips due to increased voltage differences and current demands, leading to inefficiencies and impedance issues that affect voltage stability and power efficiency.
Innovation Solution
A system is implemented with multiple power supplies located on different sides of the chip, each connected to a preceding-stage power supply, to reduce line impedance and volume of post-stage power supplies, improving dynamic response and frequency characteristics by distributing performance needs across multiple power supplies with different output impedances and operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single post-stage power supply is used to supply power to the chip, then the structure is simple, but the transmission impedance is high and dynamic response performance is poor
Solution Approach 1:
The patent divides the single post-stage power supply into multiple power supplies (first post-stage power supply and second post-stage power supply) positioned at different sides of the chip. Each power supply independently supplies power to its respective side, reducing the transmission impedance and improving voltage stability during dynamic operations.
2Loss of energy
If the bus voltage is increased to 48V or 400V to reduce transmission loss, then power efficiency improves, but the voltage difference between input and output of the power supply increases
Solution Approach 1:
The patent employs a two-stage power conversion architecture where the first power supply converts high-voltage input (48V/400V) to an intermediate voltage, and the second power supply converts the intermediate voltage to the final low-voltage output. This segmentation of voltage conversion stages manages the voltage difference more effectively while maintaining power efficiency.
Solution Approach 2:
The first post-stage power supply acts as an intermediary by converting the high-voltage input from the first power supply to a lower intermediate voltage before the second post-stage power supply converts it to the final output voltage. This intermediate conversion stage reduces the voltage stress on individual power supply components.
3Adaptability or versatility
If the supply voltage is reduced to meet lower process node requirements (e.g., 0.6V for 10nm), then compatibility with advanced processes improves, but the power supply current must increase to maintain power requirements
Solution Approach 1:
The patent positions power supplies at different sides of the chip (first post-stage power supply at one side, second post-stage power supply at another side) to distribute the high current requirements locally. This spatial segmentation reduces the current density in individual power supply paths and improves power delivery efficiency to different functional blocks of the chip.
4Object-generated harmful factors
If multiple post-stage power supplies are positioned far from the chip to reduce interference with high-speed signal lines, then signal integrity improves, but the transmission impedance increases
Solution Approach 1:
The patent positions the first post-stage power supply at a first side of the chip and the second post-stage power supply at a second side of the chip, both within close proximity. This segmented positioning allows each power supply to serve its local area with low transmission impedance while the overall layout minimizes interference with high-speed signal lines through proper spatial arrangement.
Data Source
AI summary
A system of providing power to a chip on a mainboard includes: a first power supply, located on the mainboard, and being configured to receive a first voltage and to provide a second voltage; and a second power supply and a third power supply, located on the mainboard and disposed at different sides of the chip, each of the second power supply and the third power supply is electrically connected to the first power supply to receive the second voltage, the second power supply provides a third voltage to the chip, the third power supply provides a fourth voltage to the chip, and ZBUS_2≤5*(ZPS2_2+ZPDN_2), ZBUS_2 is bus impedance between the first power supply and the third power supply, ZPS2_2 is equivalent output impedance of the third power supply, and ZPDN_2 is transmission impedance between the third power supply and the chip.