Neural Network Chip Power Prediction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for predicting power usage of a chip are inaccurate, leading to repeated design phases and resource wastage when actual power usage measurements do not meet goals, as they require revisiting all phases of chip design after placement, clocking, and routing.
Innovation Solution
A neural network is employed to predict power usage by receiving placement data of logical components within a chip, determining routing data, and estimating power usage before the clocking and routing phases, allowing for redesign only during the placement phase if specifications are not met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power usage is measured after placement, clocking, and routing phases, then accurate power usage data is obtained, but all phases must be repeated resulting in loss of manpower and resources
Solution Approach 1:
The neural network model performs preliminary prediction of power usage during the placement phase, before clocking and routing are completed. This allows designers to evaluate power consumption early in the design process and make modifications to placement, clocking, or routing configurations without having to repeat all subsequent phases, thereby reducing time loss while maintaining measurement accuracy through sophisticated AI-based estimation
2Loss of time
If existing solutions are used to estimate power usage before full design and testing, then time is saved, but the accuracy of power usage estimation is insufficient
Solution Approach 1:
The patent replaces traditional mechanical measurement methods with a neural network-based AI system. The neural network processes placement data, clocking information, and routing details to generate accurate power usage predictions early in the design process. This substitution enables both time savings and high accuracy by using sophisticated machine learning algorithms rather than conventional estimation techniques
3Reliability
If chip design is modified after power usage measurement fails to meet goals, then power usage requirements are not met, but all phases must be repeated resulting in resource wastage
Solution Approach 1:
The neural network provides continuous feedback on predicted power usage during the placement phase, allowing designers to evaluate whether power usage goals will be met before completing all design phases. This feedback mechanism enables early detection of potential issues and allows for targeted modifications to placement, clocking, or routing configurations, ensuring power usage requirements are met while avoiding unnecessary repetition of all design phases and reducing resource wastage
Data Source
AI summary
Predicting power usage of a chip may include receiving placement data describing a placement, within the chip, of a plurality of logical components of the chip; providing the placement data as an input to a neural network; and determining, by the neural network, based on the placement data, a predicted power usage of the chip.