Chip Probing Fail Bit Prediction Using Adjacent Repair Records

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Solution Overview

Problem

The existing methods for probing wafers are inefficient due to the manual screening of micron-grade or nanometer-grade circuit wirings, leading to low chip probing efficiency and affected yield and acceptance rate of wafer products, as new fail bits often occur after general repair.

Innovation Solution

A processing method for chip probing data that involves determining new fail bits, acquiring repair records of these bits and adjacent bits, analyzing attribute information, and using classification learning to create a fail bit prediction model for predicting future fail bits, thereby enhancing probing efficiency and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual screening methods are used for probing micron-grade or nanometer-grade circuit wirings, then measurement precision can be maintained, but productivity is significantly reduced

Engineering Contradiction:
Improvedetection precisionVSAvoidchip probing efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent replaces manual mechanical screening with an automated optical detection system. The probe card incorporates optical detectors that automatically detect fail bits through optical signals, eliminating the need for manual microscopic examination while maintaining detection precision for micron-grade circuits.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system enables self-detection of fail bits through automated optical scanning. The probe card automatically identifies defective bits during the probing process without requiring external manual intervention, thereby improving productivity while maintaining measurement precision through consistent automated detection.

Inventive Principle:
Principle #25Self-service

2Reliability

If general repair is performed on all fail bits, then reliability of repaired chips is improved, but loss of time increases due to extensive probing required

Engineering Contradiction:
Improveyield and acceptance rateVSAvoidprobing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary detection of fail bits using automated optical scanning before the general repair process. By identifying all fail bits in advance through efficient automated probing, the system prepares comprehensive repair data that enables faster subsequent repair operations, reducing overall processing time while ensuring all defective bits are addressed for improved reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where detection results from automated probing are immediately fed into the repair process. The probing system continuously monitors and provides real-time information about fail bit locations and patterns, enabling dynamic adjustment of repair strategies and reducing unnecessary probing time while maintaining high reliability through comprehensive defect coverage.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11837309B2Processing method of chip probing data and computer-readable storage medium
Publication Date: 2023.12.05 CHANGXIN MEMORY TECH INC
  • US11837309B2 patent drawing
  • US11837309B2 patent drawing
  • US11837309B2 patent drawing

AI summary

A processing method of chip probing data includes: determining a new fail bit generated in an already completed chip probing process; acquiring repair record of the new fail bit, and repair records of bits adjacent to the new fail bit; analyzing the repair records to determine attribute information of the new fail bit and the adjacent bits, the attribute information including at least one of address information, redundant circuit information, element pattern of the new fail bit and chip probing flow; performing classification learning according to the attribute information to acquire a fail bit prediction model; and predicting fail bits to be chip-probed through the fail bit prediction model.