Chip Protection Envelope for Embedded Semiconductor Die
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Solution Overview
Problem
Existing methods for reliably embedding semiconductor devices within printed circuit boards face challenges in providing adequate mechanical and electrical protection during handling and integration, particularly due to the thinness and fragility of semiconductor dies.
Innovation Solution
A chip protection envelope is created with a first dielectric layer having a decomposition temperature of at least 180°C, a semiconductor die embedded within, and a conductive layer with a thickness at least one-third of the dielectric layer, providing mechanical support and robust electrical connections. This envelope includes a photodefinable polymer composition for structural integrity and adhesion, and a conductive layer for secure coupling to the semiconductor die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a semiconductor die is embedded directly into a printed circuit board, then integration efficiency is improved, but mechanical robustness and electrical protection deteriorate due to the thinness and fragility of the semiconductor die
Solution Approach 1:
The protection structure is divided into multiple functional layers: a first dielectric layer for mechanical support and adhesion, a second dielectric layer for structural protection, and a conductive layer for electrical connection. This segmentation allows each layer to perform its specific function optimally while collectively providing robust protection for the embedded semiconductor die
Solution Approach 2:
The patent employs composite material structures where a photodefinable polymer composition is combined with conductive materials and dielectric layers. This composite approach creates a multi-functional envelope that simultaneously provides mechanical strength, electrical connectivity, and thermal stability, resolving the contradiction between integration efficiency and mechanical robustness
2Reliability
If the conductive layer thickness is increased to provide robust electrical connections, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The conductive layer is applied selectively only in regions where electrical connection is required, rather than as a uniform thick layer across the entire device. This localized application provides robust electrical connectivity at the contact points while maintaining overall structural simplicity and avoiding unnecessary complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The chip protection envelope enhances the mechanical robustness and electrical connectivity of semiconductor dies during handling and embedding, reducing the risk of damage and improving integration efficiency within printed circuit boards by providing additional thickness and structural support.
Implementation Method 1
a second dielectric layer arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition
Data Source
AI summary
In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2≥t1/3.