Chip PUF Layout Using CT Fin Boundary WFM Variability
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Solution Overview
Problem
Existing technologies face challenges in generating and managing physical unclonable functions (PUFs) on-chip, which are essential for unique device identification and security in electronic devices.
Innovation Solution
The implementation of a semiconductor chip with a substrate and non-planar devices, where a gate cut passing (CT) fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness, creating a physical unclonable function (PUF) region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate cut passing (CT) fin is formed at the boundary to define transistors, then device identification and security are improved through random WFM thickness distribution, but manufacturing precision is worsened due to variability in WFM thickness affecting transistor performance
Solution Approach 1:
The patent intentionally changes the parameter of gate cut position to be at the boundary (CT fin) rather than at a standard position. This boundary positioning creates variable WFM thickness across different transistor regions, which is then used as the security feature. The parameter change from standard positioning to boundary positioning enables the random distribution pattern needed for PUF while accepting the resulting manufacturing variability.
2Reliability
If multiple non-planar devices are fabricated at the boundary with varying WFM thickness, then unique device identification is improved through random distribution, but device complexity is worsened due to mixed population of FETs meeting and failing ground rule
Solution Approach 1:
The patent introduces asymmetry by positioning the gate cut at the boundary rather than symmetrically in the center of the fin structure. This asymmetric positioning causes the work function metal to have different thicknesses on different sides of the gate cut, creating an asymmetric distribution pattern. This asymmetry is the fundamental source of the random unique identification pattern while naturally creating a mixed population of devices with different characteristics.
Data Source
AI summary
Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.