Semiconductor Chip PUF Circuit Using Inverter Threshold Variation
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Solution Overview
Problem
Current methods for generating unique identification keys for semiconductor chips are costly and complex, and existing solutions fail to ensure irreproducibility and uniqueness across chips manufactured using the same process.
Innovation Solution
A semiconductor chip design that utilizes process variations to generate a unique and irreproducible digital value by comparing logic thresholds of two inverters, where the logic thresholds are different due to manufacturing process variations, allowing for the creation of a stable and unique identification key.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware or software methods are used to generate identification keys, then unique identification can be achieved, but development and production costs increase
Solution Approach 1:
The semiconductor chip automatically generates its own unique identification key during the manufacturing process by utilizing inherent process variations in identical circuit elements. The system does not require external software intervention or additional hardware components for key generation - the identification key is self-generated from natural manufacturing variations, thereby reducing development and production costs while ensuring uniqueness
Solution Approach 2:
The invention changes the approach from using external software/hardware systems to utilizing intrinsic physical parameter variations (process variations) that naturally occur during semiconductor manufacturing. By measuring and comparing parameters such as threshold voltages of identical circuit elements, the system generates unique identification keys without requiring additional complex systems
2Reliability
If process variations are utilized to generate identification keys, then uniqueness and irreproducibility are achieved, but measurement precision requirements increase
Solution Approach 1:
The invention introduces a comparator circuit as an intermediary that compares the logic thresholds of two identical circuit elements. Rather than requiring absolute precision measurements of each element's threshold, the comparator directly compares them to determine which has the higher threshold, thereby generating the identification key. This intermediary approach reduces the measurement precision requirements while ensuring uniqueness
3Ease of manufacture
If multiple identification elements are formed with the same arrangement, then manufacturing simplicity is maintained, but measurement precision is required to detect process variations
Solution Approach 1:
The comparator serves as an intermediary that simplifies the measurement process. Instead of requiring high-precision absolute measurements of physical amounts such as threshold voltages, the comparator directly compares two identical circuit elements and outputs a binary result indicating which element has the higher threshold. This maintains manufacturing simplicity while achieving the necessary measurement capability through relative comparison
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the generation of identification keys, ensures they remain constant post-manufacturing, are unique across chips, and provide high security due to physical duplication impossibility, thereby reducing production costs and enhancing security.
Implementation Method 1
the first logic threshold is different from the second logic threshold due to a process variation
Data Source
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AI summary
Provided is a semiconductor chip to generate an unique identification key. The semiconductor chip (100) includes a first inverter (110) having a first logic thresholdpa second inverter (120) having a second logic threshold, and a first switch (130). The first switch (130) includes a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to a first input voltage value. An input terminal of the first inverter (110), an output terminal, and the first terminal of the first switch (130) are connected to a first node (101 ). An output terminal of the first inverter (110), an input terminal of the second inverter (120), and the second terminal of the first switch (130) are connected to a second node (102). A second switch (150) and a third switch (140) may also be embodies using a transmission gate TG.