Chip Quality Modeling for Selective System-Level Testing
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Solution Overview
Problem
Semiconductor testing, particularly system-level testing (SLT), is time-consuming, costly, and faces challenges such as complex test development, accessibility issues, debugging complexity, incomplete test coverage, and prolonged test times, which affect production throughput and efficiency.
Innovation Solution
Implementing a chip quality model, potentially a machine learning model, to analyze chip quality characteristics during early testing phases, recommending chips for either bypassing SLT or proceeding to SLT based on their probability of passing, thereby optimizing the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If system-level testing (SLT) is performed on all chips, then testing reliability is improved, but testing time and production throughput are worsened
Solution Approach 1:
The patent applies preliminary action by performing early quality assessment on chips using machine learning models during initial testing phases. This preliminary evaluation predicts which chips are likely to pass SLT, allowing the system to pre-identify candidates for bypassing the full SLT process, thus reducing overall testing time while maintaining reliability for chips that need comprehensive testing
Solution Approach 2:
The patent implements local quality by applying different testing strategies to different chips based on their individual quality characteristics. Instead of uniform testing, the system evaluates each chip's specific features and applies tailored testing approaches - full SLT for uncertain chips and bypass for high-confidence chips - thereby optimizing the balance between reliability and testing time
2Reliability
If system-level testing (SLT) is performed on all chips, then testing completeness is improved, but productivity is worsened
Solution Approach 1:
The machine learning model performs preliminary quality assessment before SLT, predicting which chips are likely to pass. This preliminary action enables the system to maintain testing completeness for chips that need it while improving productivity by bypassing SLT for chips with high predicted pass rates, thus resolving the contradiction between testing completeness and production throughput
Solution Approach 2:
The patent applies partial action by performing SLT only on chips that require comprehensive testing based on early quality indicators. Instead of applying full SLT to all chips (excessive action), the system selectively applies testing only where necessary, thereby maintaining adequate testing completeness while significantly improving production throughput
3Loss of time
If early quality assessment is performed using machine learning models, then testing time is reduced, but measurement precision may be worsened
Solution Approach 1:
The system implements feedback by using early test results and quality characteristics as input to the machine learning model, which then predicts SLT pass probability. This feedback loop allows the model to continuously improve its precision by learning from actual SLT outcomes, ensuring that the reduced testing cycle time does not compromise quality assessment accuracy
Solution Approach 2:
The patent replaces the mechanical/physical SLT process with a machine learning-based prediction system for initial quality assessment. This substitution uses computational models instead of physical testing to quickly evaluate chip quality, dramatically reducing testing time while maintaining acceptable precision through continuous model training and validation
Data Source
AI summary
Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.