Semiconductor Package Wire Bonding Between Stacked Chips and RDLs
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Solution Overview
Problem
Existing semiconductor packages face challenges in establishing reliable electrical connections between stack semiconductor chips and redistribution structures, particularly due to the complexity and inefficiency of current bonding methods, which can lead to high defect rates and prolonged processing times.
Innovation Solution
A semiconductor package design that includes a first stack semiconductor chip with a sub-chip and a second sub-chip of a different type, bonded using internal connection terminals, with a redistribution structure and bonding wire connecting the sub-chips, and a molding layer to seal and secure the connection, replacing traditional metal pillars with bonding wires for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metal pillars are used for electrical connection between stack semiconductor chips and redistribution structures, then the electrical connection can be established, but the bonding process becomes complex and defect rates increase
Solution Approach 1:
The patent removes the metal pillar component from the electrical connection structure and replaces it with a wire bonding approach. The wire is directly bonded to the bonding pad on the semiconductor chip and extends to the redistribution structure, eliminating the need for metal pillars and their associated complex bonding processes while maintaining electrical connectivity
Solution Approach 2:
The bonding wire serves as an intermediary element that establishes electrical connection between the semiconductor chip and the redistribution structure. This wire intermediary simplifies the bonding process by providing a direct, flexible connection path that avoids the complexity of metal pillar fabrication and integration
2Reliability
If traditional bonding methods are used to connect stack semiconductor chips, then electrical connection is achieved, but processing time is prolonged
Solution Approach 1:
The bonding pads are pre-formed on the semiconductor chip before chip stacking, and the wire bonding structure is designed in advance to connect these pads to the redistribution structure. This preliminary preparation enables faster assembly and reduces processing time during the actual stacking and bonding operations
Solution Approach 2:
The patent replaces complex mechanical bonding processes with a simplified wire bonding approach. The wire bonding method requires less precise alignment and fewer processing steps compared to traditional metal pillar bonding, thereby reducing processing time while maintaining connection reliability
3Adaptability or versatility
If bonding pads are connected with reduced pitches, then higher integration is achieved, but connection difficulty increases
Solution Approach 1:
The wire bonding approach transitions the connection from a planar, direct-pad-to-pad method to a three-dimensional structure where the wire can route connections in multiple dimensions. This allows bonding pads with reduced pitches to be connected by routing wires around obstacles or through available space, making the manufacturing process easier despite higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a reliable and efficient electrical connection between the redistribution structures, reducing defect rates and processing time, while allowing for easier connection of bonding pads, even with reduced pitches.
Implementation Method 1
a bonding wire electrically connecting the second redistribution structure to the first redistribution structure
Implementation Method 2
a first molding layer sealing the second sub-chip on the first sub-chip
Implementation Method 3
a second molding layer sealing, on the second redistribution structure, the chip structure and the bonding wire
Data Source
AI summary
A semiconductor package includes a chip structure including a first stack semiconductor chip, which includes a first sub-chip and a second sub-chip that is bonded to the first sub-chip and is of a different type from the first sub-chip, a first molding layer configured to mold the second sub-chip on the first sub-chip, and a first redistribution structure arranged above the first stack semiconductor chip and the first molding layer, a second redistribution structure arranged under the chip structure and bonded to the chip structure, a bonding wire electrically connecting the second redistribution structure to the first redistribution structure, and a second molding layer configured to seal, on the second redistribution structure, the chip structure and the bonding wire.