Chip Side-by-Side Packaging with Redistribution Structure
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Solution Overview
Problem
In 3D integrated packaging, the superposition of dies to shorten signal paths leads to dissipation problems and high process costs due to the complexity of through silicon via processes.
Innovation Solution
A chip design featuring multiple packaging function modules placed side by side on a carrier with a redistribution structure that includes independent redistribution and interconnect metal layers, avoiding die superposition and using insulation materials and underfill to manage heat dissipation, while maintaining short signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If 3D integrated packaging with superposition of WLPs is used to shorten signal paths, then the length of signal path between dies is reduced, but dissipation problems become severe
Solution Approach 1:
The patent transitions from vertical stacking (3D superposition) to lateral arrangement (side-by-side placement) of dies on the carrier. This dimensional change maintains short signal paths through the redistribution structure while eliminating the severe dissipation issues caused by stacked WLPs, as heat can dissipate more effectively from laterally arranged dies
2Length of moving object
If through silicon via process is used in 3D packaging, then signal path length is reduced, but process complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the through silicon via process from the packaging architecture. Instead of creating vertical interconnects through stacked dies, the invention uses a redistribution structure with metal layers that route signals laterally between side-by-side dies, thereby reducing process complexity and cost while maintaining short signal paths
3Temperature
If multiple dies are packaged side by side, then dissipation problems are avoided, but signal path length may increase
Solution Approach 1:
The patent introduces a redistribution structure as an intermediary between side-by-side dies. This structure, comprising multiple metal layers and interconnect elements, enables short signal paths laterally across the carrier while maintaining the thermal benefits of lateral die arrangement. The redistribution structure acts as a mediator that achieves both electrical and thermal performance goals
Data Source
AI summary
The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.