Semiconductor Chip Reinforcement Structure for Crack Control
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Solution Overview
Problem
Conventional semiconductor chip dicing and mounting processes lead to microscopic fractures and crack propagation due to mechanical and thermal stresses, which conventional crack stops fail to adequately address, especially near the chip's edges and corners, and do not effectively resist solder joint strains caused by differing thermal expansion rates between the chip and substrate.
Innovation Solution
A reinforcement structure comprising pillars or a ring is coupled to the semiconductor chip and substrate, positioned outside the electrical interconnects, to prevent crack propagation and resist thermal expansion-related stresses, combined with an underfill material to mitigate thermal strain differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional crack stops are used to prevent crack propagation, then some crack protection is provided, but the crack stops do not extend to the edges of the die allowing cracks to propagate significant distances before encountering protection
Solution Approach 1:
The crack stop structure is segmented into multiple portions: a first portion extending from the die edge inward, and a second portion extending from the die edge in a different location. These segmented portions work together to block crack propagation paths that would otherwise travel significant distances through the die.
Solution Approach 2:
The crack stop structure is extended into the vertical dimension by forming it as a three-dimensional structure that protrudes from the die surface. This adds height as a new dimension, creating a more effective barrier that cracks must overcome, rather than relying solely on planar coverage.
2Reliability
If conventional crack stops are used to protect against crack propagation, then some protection is provided, but the crack stops provide little resistance to solder joint strain caused by thermal expansion differences
Solution Approach 1:
The crack stop structure is formed as a composite featuring both a reflective layer and an absorptive layer. The reflective layer provides crack blocking functionality, while the absorptive layer dampens vibrations and absorbs stress energy from thermal expansion, providing composite functionality that addresses both crack protection and strain resistance.
Solution Approach 2:
The crack stop structure is designed to perform multiple functions simultaneously: blocking crack propagation, damping vibrations from acoustic wave devices, and absorbing thermal expansion stresses. This multi-functional design eliminates the need for separate components for each protective function.
3Reliability
If the crack stop extends close to the edges of the die to prevent crack propagation, then crack protection is improved, but the electrical interconnects positioned near the edges may be compromised or the manufacturing complexity increases
Solution Approach 1:
The crack stop structure is positioned locally at specific high-risk locations such as die corners and edges where cracks are most likely to initiate and propagate. Rather than covering the entire die surface, the crack stop is strategically placed only where needed, reducing material usage and manufacturing complexity while maintaining effective protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reinforcement structure effectively prevents crack propagation into the chip's interior and enhances the mechanical strength of solder joints by resisting thermal expansion-related stresses, thereby protecting the chip's circuit structures and improving the reliability of semiconductor chip packages.
Implementation Method 1
high solder joint stresses caused by differing thermal strain rates in the chip versus the substrate to which it is attached
Data Source
AI summary
Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate wherein the semiconductor chip has a first side facing toward but separated from a second of the substrate to define an interface region. An array of electrical interconnects is provided between the semiconductor chip and the substrate positioned in the interface region. A reinforcement structure is coupled to the first side of the semiconductor chip and the second side of the substrate and in the interface region while outside the array of electrical interconnects. An underfill is provided in the interface region.