Chip Repackaging Structure With Conductive Pillars for Heat Dissipation
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Solution Overview
Problem
The challenge in semiconductor chip packaging is to achieve high-density interconnection with improved mechanical bonding reliability and heat dissipation while maintaining a small size, as existing solutions are expensive and limited by physical constraints.
Innovation Solution
A repackaging structure that includes a substrate with corresponding pads and mounting pads, a dielectric body covering a chip, and conductive pillars connecting an electrical element to the substrate, allowing for additional functions and heat dissipation while maintaining the original input and output status of the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high density interconnection substrate is used for semiconductor chip packaging, then the bonding reliability and heat dissipation are improved, but the cost increases and the space occupation increases
Solution Approach 1:
The patent divides the packaging structure into functional segments: the original chip, the substrate with corresponding pads, and the dielectric body with electrical elements. This segmentation allows each component to be optimized independently, reducing overall cost while maintaining reliability.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support for the chip, establishes electrical connections through corresponding pads, and enables heat dissipation pathways. The dielectric body simultaneously provides electrical insulation and houses additional electrical elements, achieving multi-functionality without proportionally increasing cost.
2Reliability
If a high density interconnection substrate is used for semiconductor chip packaging, then the bonding reliability and heat dissipation are improved, but the space occupation increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking the dielectric body above the substrate plane. Electrical elements are positioned in the third dimension rather than spreading horizontally, allowing improved reliability through additional connection points without proportionally increasing the footprint area.
Solution Approach 2:
The electrical elements are nested within the dielectric body structure, which itself is positioned above the substrate. This nested arrangement consolidates multiple functional elements into a compact vertical configuration, improving reliability without linearly increasing overall volume.
3Adaptability or versatility
If additional electrical elements are added to the repackaging structure, then the functions are enhanced and heat dissipation is improved, but the device complexity increases
Solution Approach 1:
The dielectric body acts as an intermediary structure that houses electrical elements and provides controlled electrical connections to the substrate. This intermediary approach allows additional functions to be integrated without directly complicating the chip-substrate interface, managing complexity through structured mediation.
Solution Approach 2:
Electrical elements are strategically positioned at specific locations on the dielectric body where they provide maximum functional benefit. Rather than uniformly distributing complexity, the patent applies electrical elements locally where needed, enhancing adaptability while concentrating complexity only in necessary regions.
4Productivity
If the chip is repackaged with additional electrical elements, then the performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The substrate is pre-configured with corresponding pads in predetermined positions before chip mounting. The dielectric body is also prepared with electrical elements positioned in advance. This preliminary preparation of connection interfaces simplifies the final assembly process and reduces the precision demands during the actual chip mounting operation.
Solution Approach 2:
The complex alignment requirements are extracted from the chip mounting process and transferred to the substrate and dielectric body preparation stages. By pre-establishing the connection geometry in these separate components, the patent isolates the precision requirements from the critical chip-substrate bonding operation, improving overall manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The repackaging structure enhances performance by adding electrical elements for heat dissipation and electromagnetic interference shielding, while maintaining a compact size and compatibility with existing chip holders or circuit boards.
Implementation Method 1
The conductive pillar electrically connects the electrical element and the substrate
Implementation Method 2
the electrical element also has the effect of dissipating heat
Data Source
AI summary
A repackaging structure includes a substrate, at least one chip, a dielectric body, an electrical element and at least one conductive pillar. The substrate includes a plate, a plurality of mounting pads and a plurality of corresponding pads. The corresponding pads and the mounting pads are disposed on opposite surfaces of the plate. The corresponding pads correspond to the mounting pads. The chip is mounted on the substrate. The chip includes a plurality of chip leads. The chip leads are mounted on the mounting pads. The dielectric body covers the chip. The electrical element is disposed on the dielectric body. The conductive pillar electrically connects the electrical element and the substrate.