Chip Resistor Multi-Layer Conductive Structure for Bonding Strength

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Solution Overview

Problem

Conventional chip resistors face challenges in maintaining bonding strength between conductive layers and preventing external gas or liquid intrusion, which can lead to insulation of the first conductive layers and degradation of the resistor's function.

Innovation Solution

The chip resistor design includes multiple conductive layers with specific edge configurations and materials, such as flake-like carbon particles and metal particles, to enhance bonding strength and protect the first conductive layers from external interference, with the third conductive layers having a stronger bonding strength with the fourth conductive layers than the second conductive layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the insulating layer covers all of the resistor layer and part of the conductive layer, then insulation performance is improved, but the bonding strength between conductive layers decreases

Engineering Contradiction:
Improveinsulation performanceVSAvoidbonding strength between conductive layers
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The conductive structure is divided into multiple layers (first conductive layer, second conductive layer, third conductive layer, and fourth conductive layer) with the insulating layer positioned between them. This segmentation allows the insulating layer to provide electrical isolation while the stacked conductive layers maintain bonding strength through their layered configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar configuration to a three-dimensional stacked structure. The conductive layers are arranged in multiple levels above and below the insulating layer, utilizing the vertical dimension to maintain bonding strength while the insulating layer provides horizontal electrical isolation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the conductive layers are exposed to external gas or liquid, then electrical conductivity is maintained, but sulfurization occurs leading to insulation and functional degradation

Engineering Contradiction:
Improveelectrical conductivityVSAvoidsulfurization from external gas
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The insulating layer creates a protected environment around the first conductive layer, shielding it from external gases containing sulfur. This isolation prevents sulfurization reactions while the stacked conductive layers maintain electrical conductivity pathways.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

Solution Approach 2:

The insulating layer acts as an intermediary barrier between the conductive layers and external harmful gases. It physically separates the conductive materials from sulfur-containing environments, preventing chemical degradation while allowing the device to function.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Strength

If the bonding strength between third conductive layer and fourth conductive layer is increased, then resistance to peeling and cracking is improved, but device complexity increases

Engineering Contradiction:
Improvebonding strength between third and fourth conductive layersVSAvoidmulti-layer conductive structure
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent combines multiple conductive layers (second and third conductive layers) and insulating layers into a single integrated structure. This merging approach achieves enhanced bonding strength and resistance to peeling/cracking while maintaining a unified device architecture rather than separate components.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11322280B2Chip resistor
Publication Date: 2022.05.03 ROHM CO LTD
  • US11322280B2 patent drawing
  • US11322280B2 patent drawing
  • US11322280B2 patent drawing

AI summary

A chip resistor includes a substrate, a resistor layer, a first conductive layer, an insulating layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The first conductive layer is electrically connected to the resistor layer. The insulating layer covers the resistor layer and the first conductive layer. The second conductive layer covers the first conductive layer and the insulating layer. The third conductive layer covers the second conductive layer and the insulating layer. The fourth conductive layer covers the second conductive layer and the third conductive layer. Bonding strength between the third and fourth conductive layer is stronger than that between the second and fourth conductive layer.