Chip Resistor Electrode Layout for Higher Resistance Stability
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Solution Overview
Problem
Conventional chip resistors face challenges in increasing resistance without compromising power tolerance, weathering resistance, or stability due to methods like reducing layer thickness or increasing winding patterns, which can lead to electrostatic discharge and thermal instability issues.
Innovation Solution
The chip resistor design reduces the size of the electrodes on the substrate's front surface, thereby increasing the area covered by the resistance layer, allowing for more complex bending curves and higher resistance values while maintaining stability and power handling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the thickness of the resistance layer is reduced to increase resistance, then the resistance value increases, but the power tolerance and weathering resistance decrease
Solution Approach 1:
The patent transitions from modifying the resistance layer thickness (one-dimensional change) to extending the current path length through winding patterns (two-dimensional spatial arrangement). By designing serpentine or meandering current paths on the substrate surface, the effective resistance increases without reducing layer thickness, thereby maintaining power tolerance and weathering resistance while achieving higher resistance values.
Solution Approach 2:
The patent employs curved and winding current paths instead of straight lines to increase the effective length of the resistance element. The serpentine or meandering patterns create extended current paths that follow curved trajectories across the substrate, increasing resistance without requiring thinner layers, thus preserving mechanical strength and environmental resistance.
2Measurement precision
If the winding pattern of the resistance layer is increased to increase resistance, then the resistance value increases, but the spacing between lines becomes too close causing thermal instability
Solution Approach 1:
The patent divides the resistance layer into multiple discrete winding segments or sections separated by insulating barriers or spacing. This segmentation prevents excessive thermal coupling between adjacent winding lines while maintaining sufficient current path length. The separated segments allow heat dissipation between sections, reducing thermal instability caused by closely spaced windings.
3Measurement precision
If the current path of the resistance layer is increased to reduce voltage difference per unit length, then the voltage difference per unit length decreases, but the cross-sectional area decreases resulting in decreased power stability
Solution Approach 1:
The patent resolves this contradiction by extending the current path in the planar dimension (across the substrate surface) rather than increasing thickness. The winding patterns distribute the voltage drop across a larger area while maintaining adequate cross-sectional area through controlled layer thickness. This approach reduces voltage difference per unit length along the current path while preserving overall power stability through sufficient conductor area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases the resistance of the chip resistor while reducing voltage differences per unit length, enhancing power stability and tolerance to environmental factors like moisture and sulfur gas.
Implementation Method 1
According to Ohm's law of resistance, the longer the current path is, the greater the resistance is
Implementation Method 2
The thermal effect of laser processing will affect the resistance layer
Data Source
AI summary
A chip resistor includes a substrate, first to fourth electrodes, a resistance layer, a resin electrode layer, first and second insulating protective layers, and first and second external electrode layers. The first and second electrodes are respectively disposed on two opposite edge areas of a front surface of the substrate. The resistance layer extends from the first electrode to the second electrode. The first insulating protective layer completely covers the resistance layer. The resin electrode layer includes first to third portions respectively covering the first and second electrodes, and a portion of the first insulating protective layer. The second insulating protective layer completely covers the third portion and partially covers the first and second portions. The third and fourth electrodes are disposed on a back surface of the substrate. The first and second external electrode layers respectively connect the first and third electrodes, and the second and fourth electrodes.