Chip Resistor Layout for ESD Stability in Miniaturized Packages
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Solution Overview
Problem
The increasing demand for miniaturized, high-power, and high-reliability chip resistor components with improved electrostatic discharge (ESD) characteristics poses challenges in maintaining precision and reliability, especially as device sizes decrease, leading to deteriorated electrical characteristics.
Innovation Solution
A chip resistor component design featuring a substrate with a resistive layer having an outermost pattern with a second region extending from a first region, where the length of the second region is 20 μm or more, enhancing ESD characteristics and power performance through laser patterning, which extends the resistor length within a limited area, reducing voltage per unit length and improving insulation breakdown resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip resistor component is miniaturized to meet weight reduction and space constraints, then the device size is reduced, but the electrical characteristics deteriorate and reliability decreases
Solution Approach 1:
The outermost pattern of the resistive layer extends in the thickness direction (one direction) of the substrate, utilizing the third dimension to increase the effective resistance path length without increasing the planar footprint. This dimensional transition allows the resistor to maintain adequate electrical characteristics while achieving miniaturization in the lateral dimensions.
Solution Approach 2:
The resistive layer is integrated within the substrate structure, with the outermost pattern nested between the first internal electrode and the other side surface of the substrate. This nesting approach maximizes the use of available space within the chip resistor component volume to accommodate the resistance path.
2Volume of moving object
If the chip resistor component is miniaturized, then the device size is reduced, but electrostatic discharge (ESD) characteristics deteriorate
Solution Approach 1:
The outermost pattern extends in the thickness direction to provide a longer ESD current path. This vertical extension increases the distance that ESD current must travel through the resistive layer, improving ESD characteristics without increasing the lateral device footprint.
3Reliability
If the resistance path length is increased to improve ESD characteristics and power performance, then the voltage per unit length decreases, but the device area increases
Solution Approach 1:
The resistance path is extended primarily in the thickness direction rather than in the lateral plane. This vertical routing of the outermost pattern allows the resistance path length to increase while the device footprint remains compact, resolving the trade-off between ESD performance and device area.
Solution Approach 2:
The resistive layer is patterned with an outermost structure that segments the resistance path into multiple regions (first region in contact with electrode, second region extending toward other side surface). This segmentation allows optimization of the resistance distribution along the thickness direction to achieve both low voltage per unit length and compact area.
Data Source
AI summary
A chip resistor component, includes: a substrate having one surface, and one side surface and the other side surface facing each other in one direction; an terminal including an internal electrode disposed on the one surface, and an external electrode disposed on the one side surface to be connected to the internal electrode; a resistive layer disposed on the one surface, and including an outermost pattern connected to the internal electrode; and a protective layer disposed on the one surface to cover the resistive layer. The outermost pattern of the resistive layer has a first region in contact with the internal electrode and a second region extending, in the one direction, from the first region towards the other side surface. A ratio of a length of the second region in the one direction to a length of the chip resistor component in the one direction is 0.02 or more.


