Chip Resistor With Multi-Layer Terminals For Space-Constrained Circuit Stability
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Solution Overview
Problem
In electronic circuits, chip resistors are prone to defects like short circuits due to external impacts, leading to secondary damage to integrated circuits, and using multiple resistors to prevent this increases space occupancy, which is undesirable in miniaturized portable devices.
Innovation Solution
A chip resistor design featuring a base substrate with separated first and second resistor layers and terminals, where third and fourth terminals are positioned between the first and second terminals to allow for different resistance values and improved mounting on a circuit board, enhancing circuit integration and reducing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple resistors are used to prevent short circuits and improve circuit stability, then reliability is improved, but area occupied by resistors increases
Solution Approach 1:
The patent combines multiple resistor elements into a single integrated chip resistor component. The chip resistor includes a substrate with multiple resistor layers arranged in different orientations, allowing multiple resistance functions to be merged into one compact component that occupies minimal space while providing circuit stability through redundant resistor elements.
Solution Approach 2:
The patent utilizes three-dimensional arrangement of resistor layers on the substrate. Instead of placing resistors side-by-side in two dimensions, the invention stacks multiple resistor layers vertically on the same substrate area, enabling multiple resistance values and configurations within a compact footprint by exploiting the third dimension.
2Reliability
If multiple resistors are used to adjust current and prevent defects, then circuit stability is improved, but device miniaturization is hindered
Solution Approach 1:
The patent merges multiple resistor functions into a single chip resistor component with integrated substrate and multiple resistor layers. This consolidation reduces the overall device volume by eliminating the need for separate resistor components and their associated mounting spaces, while maintaining circuit stability through the multi-layer resistor structure.
Solution Approach 2:
The patent implements a nested structure where multiple resistor layers are embedded within a single substrate. The resistor layers are arranged in a compact, space-efficient configuration within the substrate volume, allowing multiple resistance elements to be nested together in a hierarchical manner that minimizes the overall device footprint.
Data Source
AI summary
A chip resistor includes a base substrate having first and second surfaces opposing each other. First and second resistor layers are separated from each other and are on the first surface of the base substrate. First and second terminals are on opposing end portions of the base substrate, respectively, and are connected to first sides of the first and second resistor layers, respectively. Third and fourth terminals are between the first and second terminals, and are respectively connected to second sides of the first and second resistor layers that respectively oppose the first sides of the first and second resistor layers.