Chip Resistor Plating Structure for Solder Crack Resistance
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Solution Overview
Problem
Chip resistors mounted on wiring substrates experience cracks due to differential thermal expansion between the chip resistor and the substrate, leading to repetitive stress on the solder bonding them, which can result in crack formation.
Innovation Solution
A chip resistor design with a substrate having an upper surface, back surface, and side surface, along with metal plating layers covering the electrodes, where the metal plating layer thickness is between 10 μm and 60 μm, reducing the stress on the solder by minimizing the difference in expansion and contraction between the chip resistor and the wiring substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the chip resistor is mounted on the wiring substrate, then the chip resistor can be used in electronic apparatuses, but the differential thermal expansion between the chip resistor substrate and the wiring substrate causes repetitive stress on the solder, leading to crack formation
Solution Approach 1:
The patent changes the physical parameter of the plating layer thickness to 10-60 μm, which is significantly thicker than conventional plating layers. This parameter change increases the plating layer's ability to absorb thermal expansion differences, thereby reducing stress on the solder joints and preventing crack formation during temperature cycling.
Solution Approach 2:
The patent uses a composite structure consisting of the substrate, electrodes, and a thick metal plating layer. The plating layer acts as a buffer zone between the chip resistor substrate and the wiring substrate, accommodating differential thermal expansion. This composite material approach allows the system to maintain both mounting capability and solder crack resistance.
2Ease of manufacture
If a conventional thin plating layer is used on the electrodes, then the manufacturing cost is lower and the structure is simpler, but the stress from thermal expansion differences causes solder cracks
Solution Approach 1:
The patent specifies a plating layer thickness parameter of 10-60 μm, which is substantially thicker than conventional plating layers. This parameter change prioritizes reliability over manufacturing simplicity, as thicker plating requires more plating material and longer plating time, but it effectively prevents solder cracks by absorbing thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively limits the formation of cracks in the solder, enhancing the reliability and durability of the chip resistor by reducing thermal stress during temperature changes.
Implementation Method 1
the substrate of the chip resistor and the wiring substrate differ from each other in linear expansion coefficient. This causes the substrate of the chip resistor and the wiring substrate to expand and contract in different manners when the ambient temperature of the electronic apparatus changes
Data Source
AI summary
A chip resistor includes a substrate, an upper electrode and a resistor body, a back electrode, a side electrode, and a metal plating layer. The substrate includes an upper surface, a back surface that intersect a thickness-wise direction and a side surface that joins the upper surface and the back surface. The upper electrode and the resistor body are formed on the upper surface. The back electrode is formed on the back surface. The side electrode is formed on the side surface. The metal plating layer includes a back plating layer and a side plating layer. The back plating layer covers at least a portion of the back electrode. The side plating layer covers at least a portion of the side electrode. The metal plating layer has a thickness that is greater than or equal to 10 μm and less than or equal to 60 μm.