Chip Resistor Recesses for Mounting Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip resistors face mounting failures due to stress concentration on solder layers when the mounting board warps, leading to potential cracking and instability in resistance values.
Innovation Solution
The chip resistor design incorporates recesses on the resistive element's lower surface, with electrodes and plating layers formed within these recesses, and a protective film between them, which reduces stress on solder layers and increases contact areas, thereby enhancing mounting strength and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrodes are disposed directly on the lower surface of the resistive element, then the manufacturing process is simple, but stress concentration occurs on solder layers when the mounting board warps, leading to mounting failures
Solution Approach 1:
The patent applies local quality by creating recesses at specific locations (where electrodes will be positioned) rather than modifying the entire resistive element surface. This localized modification provides stress relief exactly where needed - at the electrode mounting areas - while keeping the rest of the structure simple and maintaining manufacturing ease.
Solution Approach 2:
The recesses are formed in advance before electrode placement, creating a cushioning structure that anticipates and prepares for the stress that will occur during mounting. This beforehand cushioning allows the solder layers to be distributed into the recesses, creating a stress-absorbing configuration that prevents mounting failures before they can occur.
2Strength
If the contact area between solder and plating layers is increased, then mounting strength is enhanced, but the device structure becomes more complex
Solution Approach 1:
The patent increases the contact area by utilizing the vertical dimension through recesses, rather than expanding the horizontal footprint. By forming recesses that extend downward into the resistive element, the solder layers can wrap around and contact plating layers on multiple surfaces (side walls and bottom), effectively increasing contact area in three dimensions without complicating the overall device layout.
Solution Approach 2:
The structure employs nesting by placing the plating layers within the recesses formed in the resistive element. The solder layers then nest around these plating layers, creating a nested configuration where multiple components occupy the same spatial envelope. This nested arrangement increases the contact area between solder and plating without requiring additional external space or structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the occurrence of mounting failures and stabilizes the resistance value by distributing stress parallel to the recess surfaces and increasing the contact area between solder and plating layers, resulting in improved reliability and performance.
Implementation Method 1
A first plating layer is disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess.
Data Source
AI summary
A chip resistor includes a resistive element, first and second electrodes disposed on a lower surface the resistive element, a protective film disposed on the lower surface of the resistive element and between the first and second electrodes. The resistive element has first and second recesses therein. The first recess extends from the lower surface along a first edge surface and does not reach an upper surface of the resistive element. The second recess extends from the lower surface along a second edge surface and does not reach the upper surface of the resistive element. The first and second electrodes are disposed between the first and second recesses. The protective film is disposed between the first and second electrodes. A first plating layer disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess. This chip resistor avoids mounting failures.