Chip Resistor Electrode Structure for Thermal Shock Resistance
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Solution Overview
Problem
Existing chip resistors face challenges with thermal shock resistance due to differences in thermal expansion coefficients between the circuit board and the insulating substrate, leading to potential cracks in solder joints. Additionally, the adhesion strength between the metal thin film layer and the stress relaxation layer is compromised, causing peeling issues and hindering effective thermal stress relaxation.
Innovation Solution
A chip resistor design featuring a rectangular insulating substrate with upper and lower surface electrodes, a resistor bridging the upper electrodes, and resin electrode layers laminated on the lower surface electrodes. The lower surface electrodes are made of metal thin film layers with exposed portions, and the external electrodes are formed through electroplating, ensuring stable adhesion and uniform plating thickness. This design enhances heat dissipation and prevents peeling of the resin electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a metal thin film layer is formed on the stress relaxation layer made of synthetic resin material, then the adhesion strength at the interface is reduced, but the thermal stress relaxation effect is improved
Solution Approach 1:
The patent applies local quality by creating different regions with different functions: the stress relaxation layer is positioned only at the central portion of the lower surface electrode, while the peripheral portion remains as metal thin film. This local differentiation allows the central region to provide stress relaxation while the peripheral region maintains strong adhesion for plating, resolving the contradiction between adhesion strength and thermal stress relaxation.
2Reliability
If the stress relaxation layer is formed to cover most of the lower surface electrode, then the thermal stress relaxation effect is improved, but the adhesion strength is reduced due to the metal thin film layer peeling off
Solution Approach 1:
The stress relaxation layer is strategically positioned only at the central portion of the lower surface electrode rather than covering the entire surface. This local quality approach ensures that the stress relaxation function is provided where most needed (central region with highest thermal stress) while preserving the metal thin film at the periphery for strong plating adhesion, thus preventing peeling while maintaining thermal shock resistance.
Solution Approach 2:
The patent uses the central portion configuration as an intermediary solution that mediates between the conflicting requirements of stress relaxation and adhesion strength. By limiting the stress relaxation layer to the central portion, it acts as a mediator that provides sufficient stress relief without compromising the overall adhesion integrity of the electrode structure.
3Reliability
If the metal thin film layer is formed on the stress relaxation layer, then the electrical conductivity is improved, but the peeling risk increases due to internal stress of plating material
Solution Approach 1:
The patent applies local quality by maintaining the metal thin film only at the peripheral portion of the lower surface electrode where adhesion strength is critical, while using the stress relaxation layer at the central portion where electrical conductivity requirements are less stringent. This spatial differentiation resolves the contradiction by providing metal conductivity where needed while avoiding peeling risks at the plating interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed chip resistor achieves improved thermal shock resistance by effectively relaxing thermal stress through the resin electrode layers and enhancing heat dissipation via the metal thin film layers. The stable adhesion and uniform plating ensure the resistor's reliability and performance even under thermal shock conditions.
Implementation Method 1
the stress relaxation layer relaxes the thermal stress acting on a solder joint portion even upon exposure of the chip resistor to the thermal shock during surface-mounting on the circuit board
Implementation Method 2
the heat generated in the resistor to be radiated from the insulating substrate to the circuit board side through the metal thin film layers and the solder joint portions
Implementation Method 3
the pair of external electrodes being made of a plating material, wherein the pair of lower surface electrodes is made of metal thin film layers formed as thin films on the mounting surface of the insulating substrate
Data Source
AI summary
A chip resistor 10 comprises: a insulating substrate 1; a pair of upper surface electrodes 2; a resistor 3; a pair of lower surface electrodes 5; a pair of resin electrode layers 6 made of synthetic resin materials containing conductive particles and laminated on the pair of lower surface electrodes 5; a pair of end face electrodes 7; and a pair of external electrodes 8, wherein the pair of the lower surface electrodes 5 is made of metal thin film layers formed as thin films on a mounting surface of the insulating substrate 1, respectively, and includes exposed portions 5a exposed from the resin electrode layers 6, respectively, and the pair of external electrodes 8 is in contact with the exposed portions 5a of the lower surface electrodes 5 and entire surfaces of the resin electrode layers 6, respectively.