Chip Routing Abstraction for Multi-Core IC Blocks
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Solution Overview
Problem
The complexity of multi-core integrated circuits poses significant challenges in chip routing, particularly due to the large number of connections, which leads to lengthy simulation times and iterative re-routing processes, consuming substantial time and resources.
Innovation Solution
The method involves creating a layout abstraction for integrated circuit blocks, determining if the number of connections exceeds a threshold, and representing common connections as a 'superbit' to reduce the number of connections for simulation, thereby speeding up the chip routing process by capitalizing on similar routing topologies and reducing computational intensity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of connections between integrated circuit blocks is increased to support multiple cores and functions, then the processing power and functionality of the IC is improved, but the simulation time and routing complexity increases significantly
Solution Approach 1:
The patent merges multiple individual connections between integrated circuit blocks into a single bundled connection representation. Instead of simulating each connection separately, the routing software treats a group of connections as one unified routing target, significantly reducing the number of routing operations and simulations required while still achieving the same functional connectivity between blocks.
Solution Approach 2:
The patent segments the routing process into two phases: first routing connections as individual targets during initial placement, then bundling remaining connections into grouped representations for final routing. This segmentation allows the system to handle both precise individual routing requirements and efficient bulk routing operations, reducing overall computational complexity.
2Area of stationary object
If the constituent blocks are packed into the smallest possible area to minimize chip size, then the area efficiency is improved, but the routing complexity and iteration time increases
Solution Approach 1:
By merging multiple connections into bundled representations, the patent reduces routing complexity even when blocks are densely packed. The bundled connections can be routed as single entities through congested areas, making it easier to achieve feasible routing solutions in compact floorplans without requiring multiple iterative redesigns.
3Adaptability or versatility
If multiple processing cores are implemented on a single IC to increase processing power, then the functionality is improved, but the number of connections and routing iterations increases
Solution Approach 1:
The patent applies connection bundling specifically to multi-core processor designs, where numerous connections exist between cores, cache, and other functional blocks. By representing groups of connections as bundled entities, the system reduces the number of routing iterations needed to establish connectivity between multiple cores, directly addressing the complexity issue in multi-core designs.
Data Source
AI summary
Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout abstract for a first block and a second block of the integrated circuit, where the first and second blocks are coupled together via a plurality of connections. The method may further include determining whether the number of connections in the plurality exceeds a threshold, and in the event that the number of connections exceeds the predetermined threshold, representing a first subset of the plurality as a first logical connection.