Semiconductor Chip Routing With Through-Chip Line Crossings
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Solution Overview
Problem
In semiconductor device production, high pin counts lead to challenges in arranging conducting lines without crossings, which can cause electrical shorts, necessitating additional metallization layers to facilitate connections between the chip and external contact elements.
Innovation Solution
Incorporating a conducting element within the semiconductor chip to enable crossings of conducting lines in a single layer by using it as a functional part of the redistribution layer, allowing connections between chip contact elements and external elements without requiring additional layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single metallization layer is used to connect contact elements to external terminals, then the device complexity is reduced, but line crossings cause electrical shorts that prevent proper routing
Solution Approach 1:
The patent introduces a vertical dimension by creating through-chip vias that penetrate the semiconductor substrate. This allows conducting lines to cross from one side of the chip to the other, enabling three-dimensional routing that resolves line crossing problems in planar single-layer designs while maintaining connection integrity.
Solution Approach 2:
The patent uses intermediary through-chip vias and intermediate conducting layers within the substrate to facilitate line crossings. These intermediaries allow signals to transition between different routing planes, enabling complex interconnections without direct line crossings that would cause shorts in a single metallization layer.
2Reliability
If additional metallization layers are added to enable line crossings, then electrical connection integrity is maintained, but the device complexity and manufacturing cost increase
Solution Approach 1:
Rather than adding more horizontal metallization layers, the patent exploits the vertical dimension by creating through-chip vias that penetrate the substrate. This three-dimensional approach enables line crossings using the same metallization layer on opposite sides of the chip, avoiding the need for additional lateral layers and reducing overall device complexity.
3Adaptability or versatility
If the number of conducting lines is increased to accommodate high pin counts, then the connectivity is improved, but line crossings and electrical shorts become more frequent
Solution Approach 1:
The patent enables high pin counts by utilizing vertical through-chip vias that allow conducting lines to cross the substrate thickness. This three-dimensional routing capacity accommodates numerous connections without increasing the density of planar lines, thereby maintaining connection integrity while supporting high connectivity requirements.
4Area of stationary object
If conducting lines are arranged densely to reduce package size, then the area is reduced, but line crossings cause electrical shorts
Solution Approach 1:
The patent reduces package area by implementing dense planar routing and utilizing vertical through-chip vias for line crossings. This combination of dense two-dimensional routing with three-dimensional crossing points allows compact packaging while maintaining electrical connection integrity through the substrate penetration approach.
Data Source
AI summary
A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.