Chip Scale Packaging Bumps with Variable Diameter Under Bump Metal
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Solution Overview
Problem
Chip-scale packaging technologies face challenges with stress and strain accumulation at solder joints between semiconductor dies and printed circuit boards due to thermal expansion differences, leading to potential cracks and reduced thermal cycling reliability.
Innovation Solution
The use of a combination of large and small solder balls on the semiconductor die, where small solder balls are placed in the outer region and large solder balls in the inner region, redistributes stress and strain, and their specific sizes and shapes after reflow ensure reliable connections and reduced crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform solder balls are used across the entire semiconductor die, then manufacturing is simpler, but stress and strain accumulation occurs at solder joints during thermal cycling
Solution Approach 1:
The patent applies local quality by using two different solder ball sizes (first size for outer region, second size for inner region) positioned at different locations on the semiconductor die. This local differentiation allows the outer solder joints to accommodate thermal expansion stress while maintaining overall manufacturing feasibility through a systematic size variation approach.
2Volume of moving object
If smaller solder balls are used to reduce package size, then form factor is reduced, but stress concentration increases at solder joints
Solution Approach 1:
The patent implements local quality by strategically placing larger solder balls in the inner region where stress concentration occurs during thermal cycling, while using smaller solder balls in the outer region to minimize package footprint. This location-specific size variation simultaneously addresses both package size reduction and solder joint strength requirements.
3Strength
If larger solder balls are used to improve connection strength, then solder joint reliability improves, but package footprint increases
Solution Approach 1:
The patent applies local quality by concentrating larger solder balls (with greater strength) only in the inner region where they are most needed for stress accommodation, while using smaller solder balls in the outer region to minimize overall package footprint. This selective size distribution optimizes both strength and area parameters.
4Manufacturing precision
If single-size solder balls are used, then manufacturing precision requirements are lower, but stress distribution during thermal cycling becomes uneven
Solution Approach 1:
The patent implements local quality by defining specific size variations for solder balls based on their position (outer vs. inner region). This approach maintains reasonable manufacturing precision by limiting size variation to two discrete sizes while achieving uniform stress distribution through the strategic placement of different sized balls at different locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the accumulative plastic strain during temperature cycling by up to 16%, enhancing the thermal cycling reliability of solder joints and preventing cracks.
Implementation Method 1
the plurality of solder balls on the chip-scale packaging based semiconductor device are aligned with the corresponding solder pads on the PCB board. By employing a hot air flow and appropriate pressure, the solder balls are heated and then melted
Implementation Method 2
the solder balls are heated and then melted so as to connect the semiconductor device with the PCB board
Implementation Method 3
The use of a combination of large and small solder balls on the semiconductor die, where small solder balls are placed in the outer region and large solder balls in the inner region, redistributes stress and strain
Data Source
AI summary
A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.