Chip Scale Packaging with Groove-Based Wafer Separation
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Solution Overview
Problem
The existing wafer level package requires a multi-cut process on the wafer, which is complex, requires high accuracy, and is prone to producing defective devices due to cumbersome cutting methods.
Innovation Solution
A chip scale package (CSP) process that involves forming a groove on the upper surface of a multi-device wafer, performing passivation and metallization treatments, and using a carrier to grind and separate the wafer into packaged devices, thereby avoiding the need for a multi-cut process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-cut process is used on the wafer, then the wafer can be divided into multiple devices, but the process becomes complicated and prone to defects
Solution Approach 1:
The patent applies segmentation by forming grooves that divide the wafer into multiple device regions. Instead of using multiple cutting passes, the wafer is pre-segmented into discrete device units defined by the groove patterns, allowing each device to be independently processed and separated without complex multi-step cutting operations.
Solution Approach 2:
The groove formation is performed as a preliminary action before the actual device separation. By pre-forming the grooves that define device boundaries and creating separation channels in advance, the subsequent device extraction becomes a simple separation process rather than requiring multiple precise cutting operations.
2Productivity
If multiple cutting operations are performed on the wafer, then devices can be separated, but the accuracy requirements become extremely strict
Solution Approach 1:
The wafer is segmented into discrete device regions by forming grooves between devices. This segmentation creates natural separation boundaries that eliminate the need for multiple high-precision cutting operations, as each device can be separated along the pre-formed groove paths with much lower precision requirements.
Solution Approach 2:
The grooves act as intermediary structures that facilitate device separation. These grooves serve as pre-created separation channels that guide the separation process, reducing the precision demands compared to direct multi-cut operations between devices.
3Productivity
If a multi-cut process is used on the wafer, then devices can be extracted, but the process is cumbersome and time-consuming
Solution Approach 1:
The grooves are formed in advance as a preliminary action that creates ready-made separation paths. This preliminary groove formation eliminates the need for time-consuming multiple cutting operations during device extraction, as separation can proceed along the pre-established groove channels.
Solution Approach 2:
By segmenting the wafer into discrete device units with grooves between them, the extraction process becomes a simple separation operation rather than requiring multiple cutting steps. This segmentation dramatically reduces the time required for device extraction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process simplifies the technological steps, reduces production costs, and improves processing efficiency by eliminating the complexity of multi-cutting, while also enhancing the flatness and collective marking efficiency of device units.
Implementation Method 1
the groove may be formed by at least one or a combination of mechanical cutting, chemical etching, plasma cutting, and laser cutting
Implementation Method 2
the groove may be formed by at least one or a combination of mechanical cutting, chemical etching, plasma cutting, and laser cutting
Implementation Method 3
the groove may be formed by at least one or a combination of mechanical cutting, chemical etching, plasma cutting, and laser cutting
Implementation Method 4
the groove may be formed by at least one or a combination of mechanical cutting, chemical etching, plasma cutting, and laser cutting
Implementation Method 5
performing a passivation treatment on the upper surface of the wafer and an inner surface of the groove to form a passivation layer
Implementation Method 6
performing a metallization treatment in the opening to form a metal bump
Implementation Method 7
the metallization treatment may be performed by electroless plating, electroplating, reballing, or chemical vapor deposition (CVD)
Implementation Method 8
the metallization treatment may be performed by electroless plating, electroplating, reballing, or chemical vapor deposition (CVD)
Implementation Method 9
the metallization treatment may be performed by electroless plating, electroplating, reballing, or chemical vapor deposition (CVD)
Implementation Method 10
the protective layer may be added by coating or attaching an inorganic material, an epoxy resin, silicone, or a polyimide (PI) film
Implementation Method 11
grinding the lower surface of the wafer to penetrate the bottom of the groove
Implementation Method 12
attaching a carrier to the upper surface of the wafer
Data Source
AI summary
A chip scale package process includes: forming a groove on an upper surface of a multi-device wafer; forming a passivation layer on the upper surface and in the groove; forming an opening of the passivation layer; forming a metal bump in the opening; adding a protective layer on the upper surface and in the groove; conducting a treatment after adding the protective layer on the upper surface and in the groove to expose the metal bump; attaching a carrier to the upper surface and grinding a lower surface of the wafer to penetrate a bottom of the groove; and forming a metal layer on the lower surface and separating the carrier from the wafer to form multiple packaged devices. The CSP process avoids the need for a multi-cut process on the surface of the wafer, thereby simplifying the technological process, reducing the production cost, and improving the processing efficiency.