Chip-Scale Logic Drive Packaging for Low-NRE Programmable ICs

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Solution Overview

Problem

The transition from Field Programmable Gate Arrays (FPGA) to Application Specific ICs (ASIC) or Customer-Owned Tooling (COT) chips is hindered by larger chip size, higher fabrication costs, lower yield, and increased Non-Recurring Engineering (NRE) costs, especially at advanced technology nodes, which slows down innovation and adoption of new semiconductor technologies.

Innovation Solution

A standardized commodity logic drive comprising plural standardized commodity FPGA/HBM CSPs and non-volatile IC chips, allowing for field programming and reducing NRE costs by a factor of up to 100, enabling innovation using advanced technology nodes like 16 nm, 10 nm, or 7 nm without the high costs associated with ASIC or COT designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If FPGA IC chip is used for a given application, then adaptability and ease of programming are improved, but chip size increases, fabrication yield decreases, and fabrication cost increases compared to ASIC or COT chip

Engineering Contradiction:

ImproveprogrammabilityVSAvoidfabrication yield

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The system segments the logic function into a separate programmable logic device (PLD) that can be independently configured. This allows the PLD to be optimized for specific applications through programming rather than requiring custom ASIC fabrication, thereby improving fabrication yield while maintaining adaptability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs universal PLDs that can be programmed to perform multiple different logic functions. This multi-functionality replaces the need for multiple specialized ASICs, improving overall fabrication yield by using a single standardized component type across different applications.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If FPGA IC chip is used for a given application, then adaptability is improved, but power consumption increases compared to ASIC or COT chip

Engineering Contradiction:

ImproveprogrammabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically configures the PLD to match the specific logic requirements of each application. By programming the PLD to implement only the necessary logic functions rather than providing all possible functions permanently wired as in ASIC, power consumption is reduced while maintaining adaptability.

Inventive Principle:

Principle #15Dynamics

3Productivity

If ASIC or COT IC chip is used to implement expanded application, then performance is improved, but Non-Recurring Engineering cost increases greatly at advanced technology nodes

Engineering Contradiction:

ImproveperformanceVSAvoidNRE cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

Instead of creating expensive custom ASICs through costly photomask sets at advanced technology nodes, the patent uses standardized PLD copies that can be programmed to replicate the desired logic function. This approach achieves the necessary performance while avoiding the prohibitive NRE costs of custom fabrication.

Inventive Principle:

Principle #26Copying

4Productivity

If advanced technology node (below 30 nm) is used for ASIC or COT design, then performance is improved, but NRE cost increases by more than US $5M due to photo mask set cost

Engineering Contradiction:

ImproveperformanceVSAvoidNRE cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent employs relatively inexpensive, programmable logic devices that can be reconfigured or replaced as applications evolve, rather than investing in extremely costly custom ASIC fabrication at advanced nodes. This approach achieves adequate performance for many applications without the million-dollar NRE investment in photomask sets.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS12354966B2Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

Publication Date: 2025.07.08 ICOMETRUE CO LTD

AI summary

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.