Chip-Scale Logic Drive Packaging for Low-NRE Programmable ASIC Replacement
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Solution Overview
Problem
The high cost and complexity of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) chips, along with increased Non-Recurring Engineering (NRE) costs for advanced semiconductor technology nodes, hinder innovation and scalability in semiconductor IC chips.
Innovation Solution
Utilizing standardized commodity logic drives comprising plural FPGA/HBM Chip-Scale Packages (CSPs) and non-volatile IC chips for field programming, reducing NRE costs and enabling innovation in advanced technology nodes through software development and cloud-based implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transitioning from FPGA to ASIC chips is implemented, then manufacturing precision and performance are improved, but device complexity and NRE costs increase significantly
Solution Approach 1:
The patent uses FPGA chips as programmable copies that can replicate ASIC functionality without requiring expensive ASIC fabrication. The FPGA serves as a reusable template that can be reconfigured for different applications, eliminating the need for costly photo mask sets and NRE investments while maintaining comparable manufacturing precision through standard semiconductor fabrication processes.
Solution Approach 2:
The patent changes the key parameter from fixed hardware implementation (ASIC) to reconfigurable software-defined implementation (FPGA). This allows the same physical chip to adapt its logic functionality through programming, effectively changing the operational parameters without requiring physical re-fabrication, thereby avoiding the high NRE costs associated with ASIC parameter changes.
2Productivity
If advanced semiconductor technology nodes are adopted, then performance and integration density are improved, but NRE costs increase exponentially
Solution Approach 1:
The patent implements a universal FPGA platform that can serve multiple applications and functions across different advanced technology nodes. The same FPGA chip architecture can be programmed to perform various logic functions, making the high integration density of advanced nodes accessible without requiring separate expensive ASIC designs for each application, thereby reducing the exponential NRE cost increase.
3Adaptability or versatility
If FPGA IC chip is used for a given application, then adaptability and development flexibility are improved, but chip size and fabrication cost increase
Solution Approach 1:
The patent applies partial action by implementing only the necessary logic functions required for a given application on the FPGA, rather than providing full programmability for all possible functions. This allows the FPGA to be optimized for specific use cases, reducing the effective chip size and fabrication cost while maintaining sufficient adaptability for the target application through selective logic implementation.
Data Source
AI summary
A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.