Carrier-Protected Chip Scale Package for Heat Dissipation
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Solution Overview
Problem
Conventional six-sided protected chip scale package (CSP) semiconductor devices face challenges in efficiently dissipating heat generated by power semiconductor devices while maintaining structural compactness and protecting the device from environmental factors.
Innovation Solution
The semiconductor device incorporates a carrier with an exposed first major surface through the moulding material, allowing for improved heat dissipation and structural integrity by acting as a heat sink, while the carrier's recessed design accommodates the semiconductor die and adhesive, reducing overall package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mould material covers all six sides of the semiconductor die, then the device is protected from environmental factors, but heat dissipation is compromised
Solution Approach 1:
The mould material coverage is segmented rather than complete - it covers five sides of the carrier but deliberately leaves the first major surface exposed. This partial coverage segmentation allows the device to gain environmental protection where needed while maintaining heat dissipation capability at the exposed surface.
Solution Approach 2:
Different regions of the device are given different levels of protection: the carrier body and semiconductor die are protected by mould material on five sides, while the first major surface of the carrier is left exposed with enhanced heat dissipation properties. This local differentiation allows simultaneous achievement of protection and heat dissipation.
2Length of stationary object
If the carrier recess is designed to receive adhesive and semiconductor die, then package height is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The carrier recess is pre-formed with specific dimensions and geometry before adhesive application. This preliminary structuring of the recess provides natural alignment features and depth control that guide adhesive placement, reducing the actual manufacturing precision required during the bonding process.
Solution Approach 2:
The carrier recess acts as an intermediary structure that mediates between the adhesive layer and the semiconductor die. It provides a controlled interface that accommodates adhesive variation and ensures consistent bonding, thereby reducing the precision requirements for adhesive application while maintaining compact package height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced heat dissipation and structural integrity without increasing the package height, making it suitable for high power transistor devices and harsh environments.
Implementation Method 1
an adhesive layer is arranged in the recess for mounting the semiconductor die to the carrier
Implementation Method 2
a moulding material partially encapsulating the semiconductor die and the carrier
Data Source
Figure 1
Figure 2a
Figure 2b~2d
AI summary
The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. In particular the disclosure relates to chip scale package semiconductor device, comprising; a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a moulding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through moulding material, and the at least two terminals are exposed through moulding material on a second side of the device.