Chip-Scale Package Device With Embedded Substrate And Insulator
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Solution Overview
Problem
Conventional chip-scale package devices face issues such as elastic deflection and solder reflow during manufacturing, leading to tilting of semiconductor chips, inadequate shielding against electromagnetic interference, and failure to meet miniature structure requirements for portable electronic devices.
Innovation Solution
A chip-scale package device design featuring a substrate unit with a receiving space for the chip and an electrical insulator that covers the chip, along with electrode pads for electrical connections, eliminating the cantilever structure and providing electromagnetic interference shielding, while allowing for improved solder reflow and adhesion strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a lead frame with cantilever structure is used to hold the semiconductor chip, then the chip can be electrically connected to external electrodes, but elastic deflection occurs during hot pressing process causing chip tilting
Solution Approach 1:
The patent removes the traditional lead frame cantilever structure that causes elastic deflection. Instead, it uses a substrate with pre-formed through-holes and electrode pads that directly support the chip, eliminating the source of deformation during hot pressing while maintaining electrical connection functionality.
Solution Approach 2:
The patent divides the electrical connection function into separate components: through-holes for vertical connections and surface electrode pads for horizontal connections. This segmentation allows independent optimization of mechanical stability and electrical connectivity, preventing the coupled deformation issues of integrated lead frames.
2Reliability
If wire bonds or solders are used for electrical connection, then electrical signals can be transmitted, but solder reflow occurs under high temperature during manufacturing
Solution Approach 1:
The patent introduces an intermediary epoxy resin material that fills the through-holes and provides mechanical support during soldering. This intermediary absorbs thermal stress and prevents solder reflow, while still allowing electrical signals to pass through the conductive epoxy paths from chip electrodes to external pads.
Solution Approach 2:
The patent uses composite epoxy resin material with conductive properties (containing metal particles or fibers) that combines the benefits of mechanical support, electrical conductivity, and thermal stress resistance. This composite material simultaneously addresses electrical connection reliability and manufacturing process stability.
3Reliability
If conventional package structure is used, then electrical connections can be established, but the device size does not meet miniature requirements for portable electronics
Solution Approach 1:
The patent transitions from a planar lead frame layout to a three-dimensional substrate structure with vertical through-holes. This dimensional change allows electrical connections to be established in the vertical direction, reducing the horizontal footprint and enabling miniaturization while maintaining connection reliability.
Solution Approach 2:
The patent embeds the chip vertically within the substrate structure, with through-holes passing through the substrate and electrode pads arranged on the surface. This nested arrangement compactly integrates the chip, connection paths, and external interfaces, minimizing the overall package volume.
Data Source
AI summary
A chip-scale package device includes a substrate unit, a chip unit, and an electrical insulator. The substrate unit has opposite first and second surfaces, and a receiving space defined by a space-defining surface. The chip unit is disposed in the receiving space, and includes a chip and first and second electrodes disposed oppositely on the chip. The electric insulator fills the receiving space to cover the space-defining surface and the chip unit and to expose the first electrode. The first and second surfaces and the space-defining surface are electrically connected to one another, and the second electrode is electrically connected to the space-defining surface.