Leadless Chip Scale Package Intermediate Pads Fabrication
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Solution Overview
Problem
The existing lead frame technologies for microelectronic devices are costly due to the need for photolithographically-defined structures and adhesion promoters, which increase fabrication complexity and costs.
Innovation Solution
A microelectronic device with leaded/leadless chip scale packaging that uses intermediate pads formed without photolithographic processes, where wire bonds connect the die to these pads, and an encapsulation material surrounds them, allowing package leads to be attached outside the encapsulation material, reducing material costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If photolithographically-defined structures and adhesion promoters are used in lead frames, then reliability is improved, but fabrication complexity and costs increase
Solution Approach 1:
The patent removes the lead frame structure entirely from the packaging system. Instead of using a traditional lead frame with photolithographically-defined structures and adhesion promoters, the invention directly mounts the die to the substrate and forms wire bonds and intermediate pads without requiring a separate lead frame component. This extraction eliminates the need for complex photolithographic processes and adhesion promoter applications while maintaining reliable electrical and mechanical connections.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support, electrical connections, and mounting structure for the die. The intermediate pads formed on the substrate serve both as electrical connection points and as structural elements for lead attachment. This multi-functionality consolidates the roles previously separated between lead frame, substrate, and bonding structures, eliminating the need for specialized lead frame fabrication processes.
2Reliability
If photolithographically-defined structures are used in lead frames, then adhesion to encapsulation material is improved, but material costs and fabrication costs increase
Solution Approach 1:
The patent eliminates the lead frame structure that would require adhesion promoters and photolithographic definition. Instead, the substrate directly provides the bonding surface for encapsulation material through standard substrate preparation processes, removing the need for additional adhesion promoter materials and photolithographic fabrication steps.
Solution Approach 2:
The invention changes the fundamental approach to achieving adhesion by transitioning from a two-layer system (lead frame with adhesion promoter) to a direct substrate-encapsulation interface. This parameter change in the structural configuration allows the use of standard substrate materials and preparation methods, reducing material costs while maintaining adequate adhesion for encapsulation.
3Reliability
If traditional leaded or leadless packages are used, then reliable packaging is achieved, but fabrication costs and complexity increase
Solution Approach 1:
The patent removes the traditional package structure (metal can, ceramic package, or plastic package with lead frame) and replaces it with a direct die-to-substrate mounting approach. This extraction of the intermediate package structure eliminates multiple fabrication steps including lead frame formation, die attachment to lead frame, wire bonding to lead frame, and package sealing, while achieving reliable packaging through direct die mounting and wire bonding to substrate.
Solution Approach 2:
The substrate is prepared in advance with appropriate bonding surfaces, intermediate pad structures, and wire bond access points before die mounting. This preliminary preparation of the substrate integrates multiple functions that would otherwise require separate lead frame fabrication steps, reducing overall fabrication complexity and cost while maintaining packaging reliability.
Data Source
AI summary
A microelectronic device, in a leaded/leadless chip scale package, has a die and intermediate pads located adjacent to the die. The intermediate pads are free of photolithographically-defined structures. Wire bonds connect the die to the intermediate pads. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Package leads, located outside of the encapsulation material, are attached to the intermediate pads. The microelectronic device is formed by mounting the die on a carrier, and forming the intermediate pads on the carrier without using a photolithographic process. Wire bonds are formed between the die and the intermediate pads. The die, the wire bonds, and the intermediate pads are covered with an encapsulation material, and the carrier is subsequently removed, exposing the intermediate pads. The package leads are attached to the intermediate pads.