Chip Scale Package Using Polymer Resin and Compression Mold
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Solution Overview
Problem
Current semiconductor packaging processes are lengthy, expensive, and constrain die size due to the use of large materials like lead frames and gold wires, limiting the efficiency and cost-effectiveness of chip encapsulation.
Innovation Solution
A method involving wafer thinning, trench etching, and the application of polymer resin and compression mold on opposing surfaces, along with metallization and solder units, to create a chip scale package that reduces material usage and allows for greater die occupancy within the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional packaging materials like lead frames and gold wires are used, then the die is protected and connected, but the package size is constrained and material costs increase
Solution Approach 1:
The patent removes traditional packaging components (lead frames, gold wires, large flags) and replaces them with a simplified structure using polymer resin encapsulation and compression molding. This extraction of unnecessary elements reduces package size while maintaining die protection through the encapsulant and electrical connection via solder balls directly attached to the die pad.
Solution Approach 2:
The patent merges multiple functions into fewer components: the polymer resin serves both as structural support and electrical insulation, the compression mold provides both encapsulation and sealing, and solder balls simultaneously provide electrical connection and mechanical attachment. This consolidation eliminates the need for separate lead frames and wire bonds, reducing overall package footprint.
2Reliability
If traditional packaging materials like lead frames and gold wires are used, then the die is protected and connected, but material costs increase
Solution Approach 1:
The patent replaces expensive traditional materials with cost-effective alternatives: polymer resin instead of gold wires, compression mold material instead of lead frames, and solder balls instead of wire bonds. These materials are less expensive while performing the required functions of protection and electrical connection, significantly reducing material costs.
Solution Approach 2:
The patent changes material parameters by selecting different substances with appropriate properties: using polymer resin with suitable mechanical strength and electrical insulation properties, compression mold material with appropriate thermal and chemical resistance, and solder balls with matched thermal expansion coefficients. These parameter changes enable cost reduction while maintaining reliability.
3Area of stationary object
If the wafer is thinned to increase die occupancy, then package efficiency increases, but wafer strength decreases
Solution Approach 1:
The patent applies polymer resin encapsulation and compression molding before final wafer thinning to provide structural support during processing. The encapsulant acts as a cushioning matrix that prevents wafer breakage during thinning operations, enabling aggressive thickness reduction to maximize die occupancy while maintaining sufficient mechanical strength through the composite structure of thinned wafer plus encapsulant.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces packaging material costs, increases die size occupancy, and prevents solder from making undesirable electrical connections, enhancing the efficiency and cost-effectiveness of semiconductor packaging.
Implementation Method 1
applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer
Implementation Method 2
applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer
Implementation Method 3
applying a metallization to areas of the first surface using the mask
Data Source
AI summary
A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.


