Chip-Scale QFN Packaging With Direct Contacts for RF Heat and Noise
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Solution Overview
Problem
Current packaging systems for high-frequency integrated circuits face challenges with thermal performance, size issues, and reprocessing difficulties due to the use of connecting wires, which also lead to noise problems and incompatibility with standard SMD bonding processes on PCBs.
Innovation Solution
A Chip-Scale QFN plastic packaging system that eliminates connecting wires by using multiple direct contact connections, a conductive back surface layer, and an on-chip protective layer to enhance thermal and electrical performance, while being compatible with standard SMD bonding processes and allowing for reprocessing on PCBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If connecting wires are used in packaging systems, then electrical connections can be established, but noise problems occur and thermal performance deteriorates
Solution Approach 1:
The patent removes connecting wires from the packaging system entirely. Instead, it uses direct contact connections where the chip makes contact with the package substrate through metallic pads and vias, eliminating the source of noise interference while maintaining electrical connectivity.
Solution Approach 2:
The patent introduces an intermediary structure consisting of metallic pads, through-vias, and conductive layers that mediate between the chip contacts and the external connections. This intermediary pathway provides both electrical connection and thermal conduction without the noise issues of traditional wires.
2Temperature
If chip size is increased to improve thermal contact, then thermal performance improves, but bending and cracking increase due to thermal expansion incompatibility
Solution Approach 1:
The patent segments the thermal conduction path into multiple smaller contact points distributed across the chip perimeter rather than requiring a large continuous contact area. This allows effective thermal transfer while keeping the chip size small and reducing mechanical stress from thermal expansion mismatches.
Solution Approach 2:
The patent employs composite packaging structures with different materials having matched thermal expansion coefficients. The package substrate and interlayer materials are selected to be compatible with the chip material, reducing thermal stress while maintaining thermal conduction pathways.
3Temperature
If direct contact connections are used, then thermal performance improves, but re-soldering becomes difficult due to very small connection areas
Solution Approach 1:
The patent extends the connection interface from a two-dimensional small pad area to a three-dimensional structure with vertical vias and lateral contact traces. This multi-dimensional connection approach provides both excellent thermal contact and sufficient surface area for re-soldering operations.
Solution Approach 2:
The patent incorporates preliminary protective coatings and structured contact surfaces during manufacturing that facilitate future re-soldering. The connection structures are pre-configured with adequate pad areas and protective layers that enable easy rework without compromising the original thermal performance.
4Temperature
If chip-on-board application is used to eliminate thermal problem, then thermal performance improves, but parasitic effects from connection wires and installation difficulty increase
Solution Approach 1:
The patent merges the electrical connection function and thermal conduction function into a single integrated structure. The same metallic pads, vias, and conductive pathways that provide electrical connectivity also serve as thermal conduction paths, eliminating the need for separate wire connections and reducing parasitic effects.
Solution Approach 2:
The patent creates universal contact structures that simultaneously perform multiple functions: electrical connection, thermal conduction, mechanical support, and stress distribution. This multi-functionality eliminates the need for separate wire bonds and reduces parasitic inductance and resistance.
5Object-affected harmful factors
If micro-coaxial connection structure is used, then interference is prevented, but packaging size exceeds chip size
Solution Approach 1:
The patent inverts the traditional approach by having the chip contacts extend directly to the package perimeter edges rather than using centralized coaxial structures. This inverted geometry provides interference shielding through distributed contact points while keeping the package size equal to or smaller than the chip size.
Solution Approach 2:
The patent employs nested conductive structures where inner contact pads are surrounded by outer shield layers, which are in turn surrounded by package substrate grounds. This nested configuration provides interference protection while maintaining a compact footprint that does not exceed chip dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high electrical and thermal performance, reduces packaging size, and facilitates reprocessing, addressing noise issues and size constraints, while maintaining reliability and compatibility with standard bonding processes.
Implementation Method 1
at least one conductive back surface layer (8), configured to establish electrical, and thermal connection between the semiconductor chip (5) and the QFN packaging base
Implementation Method 2
at least one conductive back surface layer (8), configured to establish electrical, and thermal connection between the semiconductor chip (5) and the QFN packaging base
Implementation Method 3
at least one protective coating (2), configured to form the outer layer of the integrated circuit package and to protect the integrated circuit against external influences
Implementation Method 4
multiple direct contact connections (9), configured to connect the semiconductor chip (5) to QFN side connections (3) and at least one QFN base connection (4)
Implementation Method 5
multiple direct contact connections (9), configured to connect the semiconductor chip (5) to QFN side connections (3) and at least one QFN base connection (4)
Data Source
AI summary
A Chip-Scale QFN (Chip Scale QFN, CSQFN) plastic packaging system is provided and is for high frequency integrated circuits with high electrical and thermal performance, that does not use connecting wires, which are inexpensive and reliable, whose connection to PCB can be reprocessed and that are compatible with standard SMD bonding processes on PCB.