Chip Integrated Structure With Scribe Lines for Dense 3D IC Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of a stacking layer in 3D ICs is poor due to large distances between adjacent functional chips, leading to a reduced number of chips per unit area and decreased integration and efficiency.
Innovation Solution
A chip integrated structure with a scribe line structure connecting and separating first dies, allowing for reduced spacing between adjacent dies, increased dies per unit area, and improved integration through a single dicing process, enhanced with seal rings and insulation layers to reduce stress and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional dicing is performed to separate functional chips, then chip separation is achieved, but the distance between adjacent chips becomes large and the number of chips per unit area is reduced
Solution Approach 1:
The patent merges the functional chip with the scribe line structure by maintaining electrical connection between them. The scribe line structure is not completely removed but retained as an electrically connected component, allowing the chip to be electrically connected to adjacent chips or substrates through the scribe line, thereby reducing the effective distance and improving integration density.
Solution Approach 2:
The scribe line structure serves as an intermediary element that provides electrical connection between adjacent chips. Instead of completely separating chips through traditional dicing, the scribe line acts as a mediator that maintains electrical continuity while still allowing physical separation, thus reducing the distance between functional elements.
2Ease of manufacture
If multiple dicing processes are used to obtain individual chips, then chip separation is achieved, but processing complexity and time increase
Solution Approach 1:
The patent performs preliminary action by maintaining the scribe line structure in a usable state during the dicing process. Instead of requiring multiple dicing steps to create separate functional chips, the scribe line is preserved as an electrically functional element, allowing subsequent processing to utilize this pre-established connection structure.
Solution Approach 2:
The scribe line structure serves multiple functions: it acts as both a physical separator during dicing and an electrical connection path between chips. This multi-functionality eliminates the need for separate connection structures, simplifying the manufacturing process and reducing the number of required processing steps.
3Reliability
If scribe line structure is completely removed during dicing, then chip separation is clean, but electrical connection between adjacent chips is lost
Solution Approach 1:
The patent converts the traditionally harmful scribe line material (which must be removed to prevent short circuits) into a beneficial electrical connection path. By treating the scribe line as a functional conductor rather than waste material to be removed, the patent transforms a potential harm into a useful feature that provides electrical connectivity.
Solution Approach 2:
The patent changes the electrical parameter of the scribe line from insulating (traditional view) to conducting (innovative view). By modifying the interpretation and treatment of the scribe line's electrical properties, the patent enables it to serve as an active electrical connection element rather than a barrier to be removed.
Data Source
AI summary
A chip integrated structure includes a package substrate and a first chip structure layer. The first chip structure layer is located on a side of the package substrate, and is electrically connected to the package substrate. The first chip structure layer includes a scribe line structure and a plurality of first dies. The scribe line structure connects the plurality of first dies and electrically separates the plurality of first dies.