Electronic Chip Seal Ring and Shared Test Pad Design
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Solution Overview
Problem
Current microchip manufacturing methods are limited in the number of chips that can be placed on a single wafer due to constraints in spacing and cutting methods, which restricts the density and efficiency of chip placement.
Innovation Solution
The proposed solution involves designing electronic chips with a seal ring and test pads that allow for closer spacing by using a particle beam cutting method, such as plasma cutting, and embedding test pads within a recess to reduce the minimum spacing between chips, enabling more chips to be manufactured on a single wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional cutting methods are used to separate chips, then chip spacing must be large to accommodate cutting tools and ensure precision, but this reduces the number of chips that can be placed on a single wafer
Solution Approach 1:
The patent replaces conventional mechanical cutting methods with a particle beam cutting method (such as plasma cutting). This substitution eliminates the need for physical cutting tools and their associated clearance requirements, enabling chip spacing to be reduced to the minimum required for electrical isolation rather than mechanical tool access. The particle beam method achieves precise separation without the tool interference that necessitated larger spacing in conventional methods.
2Productivity
If test pads are placed outside the seal ring, then each chip requires dedicated test pads, but this increases the area per chip and reduces wafer capacity
Solution Approach 1:
The patent merges the test pad function across multiple adjacent chips by placing shared test pads in the spacing regions between chips rather than dedicating separate test pads to each chip. This allows a single test pad to serve multiple chips during testing, thereby reducing the total area required for test structures and increasing the number of chips that can be manufactured on a single wafer.
Solution Approach 2:
The test pads are designed to serve multiple functions and multiple chips simultaneously. A single test pad structure performs electrical testing for several adjacent chips, making the test pad resource universal rather than chip-specific. This multi-functionality reduces the overall test structure area and increases wafer utilization.
3Productivity
If chip spacing is reduced to increase wafer capacity, then cutting precision and chip individualization become more difficult, but this is necessary to manufacture more chips per wafer
Solution Approach 1:
The patent replaces mechanical cutting with particle beam cutting (plasma cutting), which maintains high precision even at reduced spacings. The particle beam method achieves clean, accurate cuts without the tool width and clearance constraints of mechanical saws, allowing precise separation of closely-spaced chips while maintaining manufacturing quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the minimum spacing between chips to 15 μm or less, allowing for increased density and efficiency in chip placement on a wafer, thereby enabling more chips to be produced on a single wafer.
Implementation Method 1
a particle beam cutting method, such as plasma cutting
Data Source
AI summary
An electronic chip includes a seal ring whose shape is contained within a rectangle, of a width equal to a maximum width of the electronic chip and a length equal to a maximum length of the electronic chip. At least one test pad is arranged at least partially within the rectangle. The test pad is shared with at least one other adjacent electronic chip.