Chip Packaging Sealing Layer for Thermal Stability
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Solution Overview
Problem
Existing chip packaging technologies face challenges with adhesive tape reliability under high temperature, leading to chip displacement and warping due to thermal expansion differences, affecting packaging yield and reliability.
Innovation Solution
A method involving mounting chips on a carrier with a sealing layer to fix their position, followed by encapsulation and rewiring, which reduces displacement and warpage by locking the chip's position and easing thermal expansion issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If adhesive tape is used to adhere the chip to the substrate wafer, then the chip can be fixed in place, but the adhesive force is insufficient under high temperature causing chip displacement
Solution Approach 1:
The patent introduces a sealing layer as an intermediary component between the chip and the substrate wafer. This sealing layer not only provides enhanced adhesion under high temperature conditions but also serves as a barrier to prevent mold flow from directly contacting the chip, thereby eliminating the root cause of chip displacement while maintaining secure bonding.
Solution Approach 2:
The patent employs composite material structure by combining the sealing layer (made of specialized adhesive material) with the substrate wafer and chip. This composite approach allows the sealing layer to provide both strong thermal-stable adhesion and protective sealing functions, overcoming the limitations of conventional single-material adhesive tapes.
2Ease of manufacture
If the chip is directly embedded in the plastic package body, then packaging is simplified, but thermal expansion differences cause warping and stress
Solution Approach 1:
The sealing layer acts as a mediator between the chip and the plastic package body during encapsulation. It provides a compliant interface that absorbs thermal expansion differences, preventing direct stress transmission that would cause warping while still allowing the chip to be embedded in the package body for manufacturing simplicity.
Solution Approach 2:
The patent changes the material parameters of the sealing layer to have thermal expansion properties that bridge the gap between the chip and the plastic package body. This parameter adjustment allows the sealing layer to accommodate thermal expansion differences, maintaining wafer flatness while enabling direct embedding in the package body.
3Ease of manufacture
If adhesive tape is used for chip adhering, then chip mounting is simplified, but mold flow impact causes chip displacement affecting rewiring
Solution Approach 1:
The sealing layer serves as a protective intermediary that shields the chip from mold flow impact during encapsulation. This allows the use of simple adhesive mounting methods while maintaining high chip position accuracy, as the sealing layer prevents the mold material from exerting direct force on the chip that would cause displacement.
Solution Approach 2:
The sealing layer provides beforehand cushioning by being formed on the substrate wafer before the encapsulation process. This pre-formed protective layer cushions the chip against the impending mold flow impact, ensuring chip position accuracy is maintained throughout the encapsulation process without requiring complex mounting techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances packaging precision, increases yield, and reduces the difficulty of handling larger carriers, allowing for more efficient and cost-effective chip packaging.
Implementation Method 1
forming an adhesive layer on the carrier; and mounting the at least one chip to be packaged on the carrier at a predetermined position by the adhesive layer
Implementation Method 2
covering a sealing material on the back surface mounted with the at least one chip to be packaged and an exposed surface of the adhesive layer by using a semiconductor process
Implementation Method 3
the sealing layer is a thermosetting insulating material or an ultraviolet curing insulating material
Data Source
AI summary
The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: mounting at least one chip to be packaged on a carrier, a back surface of the chip to be packaged facing upwards and an active surface facing towards the carrier; forming a sealing layer, the sealing layer being at least wrapped around the at least one chip to be packaged; forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the sealing layer; detaching the carrier to expose the active surface of the at least one chip to be packaged; and completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged. The active surface of the chip to be packaged is mounted on the carrier, and the chip to be packaged is fixed on the carrier at a predetermined position by the sealing layer, so that the position of the chip to be packaged in the subsequent process is not easily moved.