Chip Security Verification Tool Tracing Data Paths
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Solution Overview
Problem
Computer chips with cyber security features face the challenge of cryptographic key leakage during communication between hardware modules, leading to potential exposure to untrusted external users, with no clear methodology to prevent such leaks.
Innovation Solution
A method and apparatus for analyzing chip designs to identify and verify the absence of leakage paths by tracing data paths from a second hardware module back to a first hardware module, determining if any data path segments exit the secure cone, and providing feedback to designers to correct potential leaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic keys are communicated between hardware modules, then the keys can be used by the second module, but the keys may be leaked to untrusted blocks or external users
Solution Approach 1:
The chip is divided into multiple hardware modules with distinct security zones. The cryptographic key storage module and the cryptographic processing module are separated, with controlled data paths between them. This segmentation prevents unauthorized access while enabling necessary key usage.
Solution Approach 2:
A secure data path with verification mechanisms acts as an intermediary between the key storage module and the processing module. This intermediary ensures that keys are transmitted only through verified, secure channels, preventing leakage to untrusted blocks.
2Adaptability or versatility
If data paths are added to enable communication between modules, then functionality is improved, but potential leakage paths are created
Solution Approach 1:
Different data paths are assigned different security qualities based on their function. Critical paths carrying cryptographic keys have enhanced security verification, while other paths have appropriate security measures. This localized security approach enables communication while minimizing leakage risks.
Solution Approach 2:
The verification mechanism provides feedback about the security state of data paths. When a potential leakage path is detected, the system can alert designers or block the communication, allowing correction before deployment.
3Reliability
If security verification is performed on chip design, then leakage paths can be detected, but the design process becomes more complex
Solution Approach 1:
Security verification is performed during the design stage rather than after manufacturing. This preliminary action identifies and corrects leakage paths before the chip is produced, avoiding costly recalls and enhancing security without adding complexity to the final product.
Data Source
AI summary
An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.