Chip Select Signal Training With Split DQ Feedback
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Solution Overview
Problem
Current chip select (CS) signal training methods in memory devices face challenges with increased data rates and frequencies, leading to issues like inter-symbol interference, cross-talk, and voltage noise, especially in DDR and LPDDR, due to insufficient alignment with the clock signal and inefficient result indication.
Innovation Solution
Implementing enhanced CS signal training by using multiple DQ pins to separately indicate results for high and low CS signal pulses, performing the training operation within a defined sampling window, and employing low-frequency entry and exit to improve alignment and reduce false failure indications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional CS signal training methods are used, then the training process is simple, but alignment accuracy with the clock signal deteriorates at increased data rates and frequencies
Solution Approach 1:
The patent segments the CS signal training by separating high pulse sampling and low pulse sampling into distinct operations. Multiple DQ pins are used to independently indicate training results for high pulses and low pulses, enabling precise alignment adjustment for each pulse type separately, which improves overall alignment accuracy at high data rates.
Solution Approach 2:
The patent implements preliminary action by performing CS signal training before normal operation begins. The training process uses a defined sampling window and low-frequency entry/exit mechanisms to prepare the signal alignment in advance, ensuring accurate synchronization is established before high-speed data transmission starts.
2Measurement precision
If multiple DQ pins are used to indicate training results separately, then alignment precision improves, but device complexity increases
Solution Approach 1:
The patent assigns different DQ pins to different functions: one DQ pin indicates training results for high pulses while another DQ pin indicates training results for low pulses. This segmentation allows the system to detect and adjust alignment precision for each pulse type independently, providing granular control over the training process.
3Reliability
If training is performed without a defined sampling window, then the process is simpler, but false failure indications increase
Solution Approach 1:
The patent establishes a defined sampling window as a preliminary control mechanism that determines when training samples are collected. This pre-defined time window ensures that sampling occurs at the correct moments relative to clock edges, preventing false failure indications by ensuring consistent and reliable sampling timing before any training evaluation begins.
Solution Approach 2:
The patent uses DQ pins to provide feedback about training status, allowing the system to detect whether alignment is successful or if adjustments are needed. This feedback mechanism, combined with the sampling window control, enables reliable training results by clearly indicating when training has completed successfully and when further adjustment is required.
4Speed
If high-frequency CS signals are used, then data transfer speed improves, but inter-symbol interference and cross-talk increase
Solution Approach 1:
The patent performs CS signal alignment training as a preliminary action before high-speed data transmission begins. By establishing accurate timing relationships between CS signals and clock edges during the training phase, the system prepares to minimize inter-symbol interference during subsequent high-frequency operation.
Solution Approach 2:
The training process uses feedback from DQ pins to detect and adjust timing relationships, allowing the system to optimize CS signal alignment specifically for high-frequency operation. This feedback-driven adjustment helps compensate for harmful effects like inter-symbol interference by fine-tuning signal timing before high-speed data transfer commences.
Data Source
AI summary
In some aspects, a memory device may receive a command to enter a chip select training mode, may perform a chip select training operation for a sampling window using a clock signal with a first frequency and a chip select signal having a pattern of high and low pulses, and may provide results of the training operation for high pulses via a first data in or out (DQ) signal and for low pulses via a second DQ signal. The memory device may receive a command to exit the chip select training mode, may process only certain commands while in the training mode, and may maintain the training results until reset by a host device. The controller may also be configured to alternate sampling on different clock edges and to reduce the frequency of the clock signal prior to exiting the training mode for improved reliability. Numerous other aspects are described.