Chip Select Signal Training Using Dual DQ Result Pins
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Solution Overview
Problem
Current chip select (CS) signal training methods in memory devices, particularly in high-speed DDR and LPDDR, face challenges such as increased complexity due to higher data rates and frequencies, leading to issues like inter-symbol interference, cross-talk, and voltage noise, with existing methods failing to accurately align CS signals with clock signals.
Innovation Solution
The implementation of enhanced CS signal training using multiple DQ pins to separately indicate results for high and low pulses of the CS signal, along with defined sampling windows and reduced clock frequencies for entry and exit, allowing precise alignment of CS signals with clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If chip select signal training is performed at higher data rates and frequencies, then data transfer speed is improved, but signal interference and alignment accuracy deteriorate
Solution Approach 1:
The patent segments the chip select signal training by separating high pulse sampling and low pulse sampling into distinct operations with dedicated sampling windows. This segmentation allows each pulse type to be sampled independently, reducing interference between samples and improving alignment accuracy even at higher data rates.
Solution Approach 2:
The patent implements preliminary actions by performing training operations at reduced clock frequencies before and after the actual high-speed data transfer. This preliminary training at lower frequencies establishes baseline alignment and allows the system to adapt to frequency changes, maintaining signal accuracy during high-speed operation.
2Device complexity
If single DQ pin is used for training results, then device complexity is reduced, but measurement precision of training results deteriorates
Solution Approach 1:
The patent segments the training result indication by using separate DQ pins for high pulse results and low pulse results. This segmentation allows precise measurement and indication of training status for each pulse type independently, improving measurement precision without requiring complex multiplexing or additional processing.
3Ease of operation
If training operations are performed at default state, then ease of operation is improved, but manufacturing precision of signal alignment deteriorates
Solution Approach 1:
The patent performs preliminary training actions at reduced clock frequencies before normal operation to establish precise signal alignment. This preliminary action ensures that the system is properly calibrated before default state operation begins, achieving both ease of operation and manufacturing precision.
Solution Approach 2:
The patent changes the clock frequency parameter during training operations, using reduced frequencies for initial alignment and then transitioning to operational frequencies. This parameter change allows the system to achieve precise signal alignment during manufacturing while maintaining ease of operation during normal use.
Data Source
AI summary
In some aspects, a system may include a host device and a memory device. The host may transmit a clock signal having a first frequency to the memory and, for a chip select training operation, transmit a chip select signal with a pattern of high pulses and low pulses. The host may initiate, for a sampling window, a chip select training operation with the memory using the clock signal and chip select signal, the sampling window including a quantity of pulses of the signal. The memory may perform the chip select training operation for the sampling window using the clock signal and chip select signal from the host. The memory may provide, via a first data in or out (DQ) pin, an indication of a result for the high pulses, and via a second DQ pin, an indication of a result for the low pulses. Numerous other aspects are described.