Semiconductor Package Chip Selection Interconnection
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Solution Overview
Problem
The existing semiconductor package structures, particularly in Package on Package (PoP) technology, face challenges in flexibility and cost due to fixed chip selection unit structures, which hinder design changes and lead to increased fabrication time and costs, as well as limitations in rearranging stacked semiconductor chips.
Innovation Solution
A semiconductor package structure and method that allows for flexible chip selection unit design by forming chip selection interconnection layers with the same structure across all chips, enabling the same photo mask usage and reducing the need for multiple photo masks, and allowing for easy reconfiguration of chip selection units during the packaging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chip selection units are designed with fixed structures determined in the chip designing process, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The patent applies dynamics by making the chip selection unit structure changeable after chip fabrication. The interconnection layers are formed with a structure that allows selective connection to different through-vias depending on the stacking order, enabling the same chip design to adapt to different package configurations without requiring redesign or new photo masks.
2Manufacturing precision
If different photo masks are used for each chip selection unit structure, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a single photo mask that can serve multiple functions for different chip selection unit configurations. The interconnection layer pattern is designed to be universally applicable regardless of which through-vias are connected, allowing the same mask to produce correct chip selection units for various stacking orders and chip combinations.
3Manufacturing precision
If chip selection units are fixed in structure, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent enables easy reconfiguration by designing interconnection layers that can be selectively connected to different through-vias based on the desired stacking order. This dynamic connectivity allows manufacturers to reconfigure chip selection units for different package configurations without changing the chip design or requiring complex manufacturing process modifications.
Data Source
AI summary
A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.