On-Chip Self-Test System for Functional Logic Modules
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Solution Overview
Problem
Integrated circuit chips with complex internal state structures and high operational speeds pose challenges for effective testing, as existing test equipment often cannot keep pace with signal frequencies and requires separate bench-top testers, leading to inefficiencies in identifying defects and ensuring functionality before assembly.
Innovation Solution
A self-test system integrated on the chip, featuring a functional logic module with primary and secondary interfaces, an emulator engine, and protocol generators/checkers, allowing for at-speed, stand-alone testing of chip functions without external devices, enabling design target speed testing and fault isolation during fabrication and in-system diagnostics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional bench-top testers are used to test chip interfaces, then comprehensive testing can be performed, but testing speed cannot keep pace with chip operational speeds and external devices are required
Solution Approach 1:
The patent merges the test system and the chip into a single integrated unit by incorporating the emulator engine and protocol generators directly onto the chip. This eliminates the need for external bench-top testers and allows testing to occur at the chip's full operational speed, resolving the contradiction between testing speed and device complexity.
Solution Approach 2:
The chip performs self-testing through the integrated emulator engine that can emulate secondary devices and generate test patterns internally. The functional logic module tests itself without requiring external test equipment, achieving self-service testing at operational speeds while reducing external device requirements.
2Reliability
If secondary devices are coupled to test interface functions, then interface functionality can be verified, but testing cannot occur during fabrication and production time increases
Solution Approach 1:
The emulator engine creates virtual copies of secondary devices internally on the chip, allowing test patterns to be applied to interface functions without requiring physical secondary devices. This copying approach enables testing during fabrication to verify interface functionality while eliminating the time loss associated with waiting for external device assembly.
Solution Approach 2:
The integrated self-test system performs interface functionality verification preliminarily during chip fabrication before the chip is assembled with secondary devices. The emulator engine executes test patterns against the functional logic module in advance, ensuring interface reliability is confirmed before final assembly, thereby reducing production time.
3Speed
If chip operational speeds are increased to improve performance, then processing capability improves, but test equipment cannot keep pace with signal frequencies
Solution Approach 1:
By merging the testing infrastructure with the chip itself, the test system operates at the same high signal frequencies as the chip's operational logic. The emulator engine and protocol generators are synchronized with the chip's internal clock domains, enabling accurate measurement and testing at full operational speeds without the bandwidth limitations of external equipment.
Data Source
AI summary
According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip.