Semiconductor Chip Sequence Checking Circuit Testability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The command/address physical layer in semiconductor chips lacks a data loopback mechanism for testing, making it difficult to ensure testability, especially when the original matching timing between the clock signal and the test data signal disappears.
Innovation Solution
Incorporating a sequence checking circuit within the semiconductor chip's physical layer, which includes a first and second shift register circuit and an output terminal logic gate, to generate a test result signal indicating the operation status of the signal transmission path, without transmitting the clock signal through the signal transmission path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a data loopback mechanism is implemented for testing the command/address physical layer, then testability is improved, but device complexity increases due to the need for additional sequence checking circuits and shift registers
Solution Approach 1:
The sequence checking circuit uses the transmitted test data signal itself as the reference for checking, rather than requiring a separate reference signal path. The circuit checks whether the received signal matches the expected sequence generated by the same pseudo-random sequence generator that created the test signal, enabling self-verification without additional external testing equipment or complex reference paths
Solution Approach 2:
The sequence checking circuit is integrated into the existing physical layer structure and can operate in both normal data transmission mode and test mode. The same circuit infrastructure (sequence generator, shift registers, logic gates) serves dual purposes: generating and checking pseudo-random sequences for testing while maintaining compatibility with standard operation, thereby reducing the need for completely separate testing hardware
2Measurement precision
If the clock signal is transmitted through the signal transmission path for timing reference, then timing accuracy is improved, but the adaptability to timing mismatches deteriorates
Solution Approach 1:
The sequence checking circuit incorporates a feedback mechanism where the received test data signal is fed back through shift registers and compared with the expected sequence. This feedback loop automatically adjusts for timing variations by using the actual received signal characteristics to determine whether the sequence matches, enabling the system to adapt to clock timing mismatches without requiring precise external timing references
Solution Approach 2:
The checking mechanism changes its operational parameters dynamically based on the received signal characteristics. By using the actual test data signal that has traversed the transmission path as the reference, the circuit adapts to variations in clock timing, signal delay, and other parameter changes that occur during transmission, rather than relying on fixed timing assumptions
3Measurement precision
If separate reference signal paths are used for testing, then measurement accuracy is improved, but the ease of operation deteriorates due to additional setup complexity
Solution Approach 1:
The patent merges the test signal generation path and the test signal checking path into a single integrated sequence checking circuit. The same pseudo-random sequence generator that creates the test signal also provides the reference sequence for checking, and the received signal is checked against this integrated reference within the same circuit block, eliminating the need for separate independent reference paths and reducing setup complexity
Data Source
AI summary
A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal and at least one test data signal transmitted through the at least one signal transmission path, and the clock signal is not transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to the voltage level of the at least one test result signal.